ARM: arch-meson: build memory banks using reported memory from registers

As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware
and a secondary BL32 firmware.
Since mid-2017, the reserved memory address of the BL31 firmware was moved
and grown for security reasons.

But mainline U-Boot and Linux has the old address and size fixed.

These SoCs have a register interface to get the two firmware reserved
memory start and sizes.

This patch adds a dynamic reservation of the memory zones in the device tree bootmem
reserved memory zone used by the kernel in early boot.
To be complete, the memory zones are also added to the EFI reserved zones.

Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2].

[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html

Changes since v1:
- switched the #if to if(IS_ENABLED()) to compile all code paths
- renamed function to meson_board_add_reserved_memory()
- added a mem.h header with comment
- updated all boards ft_board_setup()

Changes since RFC v2:
- reduced preprocessor load
- kept Odroid-C2 static memory mapping as exception

Changes since RFC v1:
- switch to fdt rsv mem table and efi reserve memory
- replaced in_le32 by readl()

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[trini: Fix warning on khadas-vim over missing <asm/arch/mem.h>
Signed-off-by: Tom Rini <trini@konsulko.com>

2 files changed, 33 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
index 95a6fe6..ef63dea 100644
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -7,10 +7,27 @@
 #ifndef __GXBB_H__
 #define __GXBB_H__
 
+#define GXBB_FIRMWARE_MEM_SIZE	0x1000000
+
+#define GXBB_AOBUS_BASE		0xc8100000
 #define GXBB_PERIPHS_BASE	0xc8834400
 #define GXBB_HIU_BASE		0xc883c000
 #define GXBB_ETH_BASE		0xc9410000
 
+/* Always-On Peripherals registers */
+#define GXBB_AO_ADDR(off)	(GXBB_AOBUS_BASE + ((off) << 2))
+
+#define GXBB_AO_SEC_GP_CFG0	GXBB_AO_ADDR(0x90)
+#define GXBB_AO_SEC_GP_CFG3	GXBB_AO_ADDR(0x93)
+#define GXBB_AO_SEC_GP_CFG4	GXBB_AO_ADDR(0x94)
+#define GXBB_AO_SEC_GP_CFG5	GXBB_AO_ADDR(0x95)
+
+#define GXBB_AO_MEM_SIZE_MASK	0xFFFF0000
+#define GXBB_AO_MEM_SIZE_SHIFT	16
+#define GXBB_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
+#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT	16
+#define GXBB_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
+
 /* Peripherals registers */
 #define GXBB_PERIPHS_ADDR(off)	(GXBB_PERIPHS_BASE + ((off) << 2))
 
diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h
new file mode 100644
index 0000000..86a8417
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/mem.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MESON_MEM_H__
+#define __MESON_MEM_H__
+
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_gx_init_reserved_memory(void *fdt);
+
+#endif /* __MESON_MEM_H__ */