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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-31 16:12:53 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 08:00:13 -0700 |
| commit | 6d9b82d085ea810c7bb2ed5203522e45cc72c336 (patch) | |
| tree | 5531a4c12ea14d5c5768e5a273b8ec3174dd2157 /arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | |
| parent | 22c51855bf79b4ef767f35067472d337858423b3 (diff) | |
| download | u-boot-6d9b82d085ea810c7bb2ed5203522e45cc72c336.zip u-boot-6d9b82d085ea810c7bb2ed5203522e45cc72c336.tar.gz u-boot-6d9b82d085ea810c7bb2ed5203522e45cc72c336.tar.bz2 | |
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index d7d527d..d1891c4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -66,12 +66,26 @@ #define FSL_USB2_STREAM_ID 2 #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 + +#if defined(CONFIG_ARCH_LS2080A) #define FSL_SATA2_STREAM_ID 5 +#endif + +#if defined(CONFIG_ARCH_LS2080A) #define FSL_DMA_STREAM_ID 6 +#elif defined(CONFIG_ARCH_LS1088A) +#define FSL_DMA_STREAM_ID 5 +#endif /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 + +#if defined(CONFIG_ARCH_LS2080A) #define FSL_PEX_STREAM_ID_END 22 +#elif defined(CONFIG_ARCH_LS1088A) +#define FSL_PEX_STREAM_ID_END 18 +#endif + /* DPAA2 - set in MC DPC and alloced by MC */ #define FSL_DPAA2_STREAM_ID_START 23 |