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author | Manish Narani <manish.narani@xilinx.com> | 2021-07-14 06:17:19 -0600 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2021-07-26 09:26:41 +0200 |
commit | 15ca9ebb074e9eca5a8264c93f5678df240fa54d (patch) | |
tree | 7c76ab72ad4f1326e1e29296e93437c147309be1 /arch/arm/dts/zynqmp-zcu111-revA.dts | |
parent | 3965d13f933d5aa670f833eb9584f119e4a11d62 (diff) | |
download | u-boot-15ca9ebb074e9eca5a8264c93f5678df240fa54d.zip u-boot-15ca9ebb074e9eca5a8264c93f5678df240fa54d.tar.gz u-boot-15ca9ebb074e9eca5a8264c93f5678df240fa54d.tar.bz2 |
arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB node
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here
the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This
PHY initialization should be handled from Xilinx USB core as the
prerequisite register configurations are done here only.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu111-revA.dts')
-rw-r--r-- | arch/arm/dts/zynqmp-zcu111-revA.dts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 8d57ca2..2b15ce1 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -849,14 +849,14 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; - phy-names = "usb3-phy"; - phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; |