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| author | Tom Rini <trini@konsulko.com> | 2022-05-25 09:50:08 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-05-25 09:50:08 -0400 |
| commit | 661f5400754750df4104b6466942c8b62897340d (patch) | |
| tree | 5ccaa46280decbe9696b58344eaedf2b2893e3cc /arch/arm/dts/zynqmp-zcu102-revA.dts | |
| parent | 7e0edcadb09d55d5319fdc862041fd1b874476f5 (diff) | |
| parent | 594f692f491f0def6c4b6543e158a7f367b35dcc (diff) | |
| download | u-boot-661f5400754750df4104b6466942c8b62897340d.zip u-boot-661f5400754750df4104b6466942c8b62897340d.tar.gz u-boot-661f5400754750df4104b6466942c8b62897340d.tar.bz2 | |
Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblazeWIP/25May2022
Xilinx changes for v2022.07-rc4
zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image
xilinx:
- Handle board_get_usable_ram_top(0) properly
phy:
- Extend psgtr timeout
mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu102-revA.dts')
| -rw-r--r-- | arch/arm/dts/zynqmp-zcu102-revA.dts | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 1b1cabb..c13b52a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -604,7 +604,26 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - /* SI5328 - u20 */ + si5328: clock-generator@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; + }; }; /* 5 - 7 unconnected */ }; @@ -948,7 +967,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ |