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| author | Tom Rini <trini@konsulko.com> | 2024-02-14 15:23:10 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-02-14 15:23:10 -0500 |
| commit | 77ff61a5bb437b5b19c50d8791f14a3b917e882c (patch) | |
| tree | ee0d8f7efd458c4246b41eb10a0d2fcdf8ffe86e /arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | |
| parent | 37345abb97ef0dd9c50a03b2a72617612dcae585 (diff) | |
| parent | c2ad5fb616d4e8aa2ac00e224030589847731fbe (diff) | |
| download | u-boot-77ff61a5bb437b5b19c50d8791f14a3b917e882c.zip u-boot-77ff61a5bb437b5b19c50d8791f14a3b917e882c.tar.gz u-boot-77ff61a5bb437b5b19c50d8791f14a3b917e882c.tar.bz2 | |
Merge tag 'xilinx-for-v2024.04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblazeWIP/14Feb2024
Xilinx changes for v2024.04-rc3
zynqmp:
- Cover missing _SE chip variants to fix fpga programming
versal:
- Enable LTO for mini configurations
versal-net:
- Enable LTO for mini configurations
- Fix GIC address to aligned with real silicon
xilinx:
- DTs cleanup and fixups
- Enable HTTP boot
- Add missing spl header to zynqmp.c
Diffstat (limited to 'arch/arm/dts/zynqmp-sck-kr-g-revA.dtso')
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 7717abf..ce7c5eb 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -25,37 +25,43 @@ io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; - si5332_0: si5332-0 { /* u17 - GEM0/1 */ + clk_27: clock0 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_125: si5332-0 { /* u17 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; - si5332_1: si5332-1 { /* u17 - DP */ + clk_74: si5332-5 { /* u17 - SLVC-EC */ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <27000000>; + clock-frequency = <74250000>; }; - si5332_2: si5332-2 { /* u17 - USB */ + clk_26: si5332-2 { /* u17 - USB */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5332_3: si5332-3 { /* u17 - SFP+ */ + clk_156: si5332-3 { /* u17 - SFP+ */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <156250000>; }; - si5332_4: si5332-4 { /* u17 - GEM2 */ + clk_25_0: si5332-1 { /* u17 - GEM2 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - si5332_5: si5332-5 { /* u17 - GEM3 */ + clk_25_1: si5332-4 { /* u17 - GEM3 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -115,7 +121,7 @@ &psgtr { status = "okay"; /* gem0/1, dp, usb */ - clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>; + clocks = <&clk_125>, <&clk_27>, <&clk_26>; clock-names = "ref0", "ref1", "ref2"; }; @@ -168,12 +174,13 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - +#if 0 usbhub1: usb-hub { /* u84 */ i2c-bus = <&usbhub_i2c1>; compatible = "microchip,usb5744"; reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_1 { |