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| author | Michal Simek <michal.simek@amd.com> | 2023-11-01 12:22:14 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-11-07 13:47:09 +0100 |
| commit | 1332a781e1ae214ee01af49454c1622cc9433517 (patch) | |
| tree | fdb8f48bcead2cec440d64d7915b258ca833d3c1 /arch/arm/dts/zynq-zc770-xm010.dts | |
| parent | 7a64be2ba259d184745147ad5163a300475b0b53 (diff) | |
| download | u-boot-1332a781e1ae214ee01af49454c1622cc9433517.zip u-boot-1332a781e1ae214ee01af49454c1622cc9433517.tar.gz u-boot-1332a781e1ae214ee01af49454c1622cc9433517.tar.bz2 | |
ARM: zynq: Add partition description
Xilinx is using standard mtd partition layout for quite a long time. It is
used for testing purpose on evaluation boards.
Also #address/size-cells shouldn't be present without nodes which should
use them that's why move them from zynq-7000.dtsi to nand/nor nodes
directly.
The patch was tested on zc706 and zedboard(with also increasing max
frequency and rx bus width).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4c3348981bba32d3892194420d78fe8621c47534.1698837725.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm/dts/zynq-zc770-xm010.dts')
| -rw-r--r-- | arch/arm/dts/zynq-zc770-xm010.dts | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 17680d7..199384b 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -69,6 +69,31 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; |