diff options
| author | Marek Vasut <marex@denx.de> | 2018-08-13 18:42:39 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-08-13 22:35:16 +0200 |
| commit | f5775e69cc201da6998dd992a93c1696e087d39a (patch) | |
| tree | e37251adfa6c27e51385b69258b1e675990289bc /arch/arm/dts/socfpga_arria10.dtsi | |
| parent | 6f96ed7e2080c305fa45e8b12d8013d8bab9ec5d (diff) | |
| download | u-boot-f5775e69cc201da6998dd992a93c1696e087d39a.zip u-boot-f5775e69cc201da6998dd992a93c1696e087d39a.tar.gz u-boot-f5775e69cc201da6998dd992a93c1696e087d39a.tar.bz2 | |
ARM: dts: socfpga: Add missing UART resets
The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/dts/socfpga_arria10.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 51b31dc..aafcfe9 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -797,6 +797,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART0_RESET>; status = "disabled"; }; @@ -807,6 +808,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART1_RESET>; status = "disabled"; }; |