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| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-04-16 22:04:39 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-04-17 22:20:16 +0200 |
| commit | 29873c74f367474faafd16376e2a9f404172fbdd (patch) | |
| tree | 774cc94f1d909f9046eea4b233d772572e5fad8b /arch/arm/dts/socfpga.dtsi | |
| parent | ede6e7b64fbd3beef691f526d14e088583f74472 (diff) | |
| download | u-boot-29873c74f367474faafd16376e2a9f404172fbdd.zip u-boot-29873c74f367474faafd16376e2a9f404172fbdd.tar.gz u-boot-29873c74f367474faafd16376e2a9f404172fbdd.tar.bz2 | |
arm: socfpga: move gen5 SDR driver to DM
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.
SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/dts/socfpga.dtsi')
| -rw-r--r-- | arch/arm/dts/socfpga.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index ec19664..51a6a51 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -791,9 +791,9 @@ reg = <0xfffec000 0x100>; }; - sdr: sdr@ffc25000 { + sdr: sdr@ffc20000 { compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; + reg = <0xffc20000 0x6000>; resets = <&rst SDR_RESET>; }; |