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| author | Christian Hewitt <christianshewitt@gmail.com> | 2020-04-24 02:58:30 +0000 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2020-07-08 10:52:45 +0200 |
| commit | da77a787ff3083ba64f848c5957fe7d4afe93508 (patch) | |
| tree | 4b5f7349ce94cf1c56c5f68972597144119534a7 /arch/arm/dts/meson-sm1.dtsi | |
| parent | 6de936b011fb02d1019a69aea0184cee4a578f59 (diff) | |
| download | u-boot-da77a787ff3083ba64f848c5957fe7d4afe93508.zip u-boot-da77a787ff3083ba64f848c5957fe7d4afe93508.tar.gz u-boot-da77a787ff3083ba64f848c5957fe7d4afe93508.tar.bz2 | |
ARM: dts: sync amlogic G12A/G12B/SM1 DT from Linux 5.8-rc1
This imports the changes and the new Odroid-C4 board from the Linux
commit b3a9e3b9622a ("Linux 5.8-rc1").
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Diffstat (limited to 'arch/arm/dts/meson-sm1.dtsi')
| -rw-r--r-- | arch/arm/dts/meson-sm1.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/dts/meson-sm1.dtsi b/arch/arm/dts/meson-sm1.dtsi index d4ec735..71317f5 100644 --- a/arch/arm/dts/meson-sm1.dtsi +++ b/arch/arm/dts/meson-sm1.dtsi @@ -56,6 +56,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -64,6 +65,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -72,6 +74,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -80,6 +83,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; l2: l2-cache0 { @@ -466,6 +470,26 @@ compatible = "amlogic,sm1-clkc"; }; +&cpu_thermal { + cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + ðmac { power-domains = <&pwrc PWRC_SM1_ETH_ID>; }; |