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| author | Neil Armstrong <narmstrong@baylibre.com> | 2019-05-28 10:50:38 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-05-31 10:04:15 +0200 |
| commit | 32f28806419797862f812c56e3148efcc716d73a (patch) | |
| tree | 79edb736292d4fe34e180fbf0bfcb7e4f40edb3e /arch/arm/dts/meson-g12a-u200-u-boot.dtsi | |
| parent | 08e09c263fdfc84abc7285f69f631d9b241716ed (diff) | |
| download | u-boot-32f28806419797862f812c56e3148efcc716d73a.zip u-boot-32f28806419797862f812c56e3148efcc716d73a.tar.gz u-boot-32f28806419797862f812c56e3148efcc716d73a.tar.bz2 | |
ARM: dts: Add missing DT for Meson G12A support
The following DT nodes in the process on review for Linux 5.3,
until Linux 5.3 is tagged, add the missing DT nodes in u-boot specific
DTSI files that will be dropped when the v5.3-rc1 DT is synced again.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'arch/arm/dts/meson-g12a-u200-u-boot.dtsi')
| -rw-r--r-- | arch/arm/dts/meson-g12a-u200-u-boot.dtsi | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/dts/meson-g12a-u200-u-boot.dtsi b/arch/arm/dts/meson-g12a-u200-u-boot.dtsi new file mode 100644 index 0000000..9486ab0 --- /dev/null +++ b/arch/arm/dts/meson-g12a-u200-u-boot.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-g12a-u-boot.dtsi" + + / { + aliases { + ethernet0 = ðmac; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_leds_pins>; + pinctrl-names = "default"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; |