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| author | Gaurav Jain <gaurav.jain@nxp.com> | 2022-03-24 11:50:34 +0530 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-04-12 11:19:21 +0200 |
| commit | 88071ca2bb80d8b59fbd3ab5ae60b4519bb40aa9 (patch) | |
| tree | 092d76f395f8e7eb56de636ffe908bdd736c514c /arch/arm/dts/ls1021a.dtsi | |
| parent | cb5d0419f5517c507685577dca41c9085b7d77c4 (diff) | |
| download | u-boot-88071ca2bb80d8b59fbd3ab5ae60b4519bb40aa9.zip u-boot-88071ca2bb80d8b59fbd3ab5ae60b4519bb40aa9.tar.gz u-boot-88071ca2bb80d8b59fbd3ab5ae60b4519bb40aa9.tar.bz2 | |
Layerscape: Add crypto node in device tree
LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/dts/ls1021a.dtsi')
| -rw-r--r-- | arch/arm/dts/ls1021a.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 86192cb..be330c1 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -3,6 +3,7 @@ * Freescale ls1021a SOC common device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include "skeleton.dtsi" @@ -144,6 +145,45 @@ big-endian; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <7>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1700000 0x100000>; + ranges = <0x0 0x1700000 0x100000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + }; + clockgen: clocking@1ee1000 { #address-cells = <1>; #size-cells = <1>; |