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| author | Jan Kiszka <jan.kiszka@siemens.com> | 2021-09-18 08:17:52 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-10-03 14:40:56 -0400 |
| commit | c3a879510a0d49355408844a8fd942224568d48d (patch) | |
| tree | 068a300f466bba33f5a5074f1be9bbbc9ec40039 /arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi | |
| parent | 903d8ede9adbd5c1956a60b01a3ec099ff3fd8b2 (diff) | |
| download | u-boot-c3a879510a0d49355408844a8fd942224568d48d.zip u-boot-c3a879510a0d49355408844a8fd942224568d48d.tar.gz u-boot-c3a879510a0d49355408844a8fd942224568d48d.tar.bz2 | |
arm: dts: Add IOT2050 device tree files
Prepares for the addition of the IOT2050 board which is based on the TI
AM65x. The board comes in four variants, Basic and Advanced, each as
product generation 1 (SR1.0) and 2 (SR2.x), so there are separate dts
files needed. Furthermore, the SPL has its own device tree.
Based on original board support by Le Jin, Gao Nian and Chao Zeng.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Diffstat (limited to 'arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi')
| -rw-r--r-- | arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi new file mode 100644 index 0000000..c25bce7 --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2021 + * + * Authors: + * Chao Zeng <chao.zeng@siemens.com> + * Jan Kiszka <jan.kiszka@siemens.com> + * + * Common bits of the IOT2050 Basic and Advanced variants, PG2 + */ + +&main_pmx0 { + cp2102n_reset_pin_default: cp2102n-reset-pin-default { + pinctrl-single,pins = < + /* (AF12) GPIO1_24, used as cp2102 reset */ + AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) + >; + }; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp2102n_reset_pin_default>; + gpio-line-names = + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "CP2102N-RESET"; +}; + +&dss { + /* Workaround needed to get DP clock of 154Mhz */ + assigned-clocks = <&k3_clks 67 0>; +}; + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0_phy { + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; |