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author | Ye Li <ye.li@nxp.com> | 2018-06-27 19:30:53 -0700 |
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committer | Stefano Babic <sbabic@denx.de> | 2018-09-04 08:47:23 +0200 |
commit | 3b82335015cc695b760c90f904ea85bae53c0597 (patch) | |
tree | 71071abb3d4c29a408c562b8ba4e5ebf58b4e4e7 /arch/arm/dts/imx7d-sdb-qspi.dts | |
parent | 0925ee21851287d48279bb43e4a0876b2005a5f2 (diff) | |
download | u-boot-3b82335015cc695b760c90f904ea85bae53c0597.zip u-boot-3b82335015cc695b760c90f904ea85bae53c0597.tar.gz u-boot-3b82335015cc695b760c90f904ea85bae53c0597.tar.bz2 |
imx: imx7d-sdb: Add DM QSPI support
On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default).
To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399
populate R392-R395, R299, R300). So we add new DTS file and new defconfig
dedicated for QSPI.
Other changes to support the DM QSPI:
- Add QSPI node and alias spi0.
- Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req
conflict
- Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to
align with kernel and also present the conflict.
- Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to
"spi-flash"
- Remove iomux settings of qspi in board codes which is not needed
for DM driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/dts/imx7d-sdb-qspi.dts')
-rw-r--r-- | arch/arm/dts/imx7d-sdb-qspi.dts | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/dts/imx7d-sdb-qspi.dts b/arch/arm/dts/imx7d-sdb-qspi.dts new file mode 100644 index 0000000..9bb4c74 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-qspi.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#include "imx7d-sdb.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25l51245g"; + spi-max-frequency = <29000000>; + /* take off one dummy cycle */ + spi-nor,ddr-quad-read-dummy = <5>; + reg = <0>; + }; +}; |