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| author | Tom Rini <trini@konsulko.com> | 2020-10-29 11:30:15 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-10-29 11:30:15 -0400 |
| commit | 47754334b164eae4fde538c406ff3678dfb05042 (patch) | |
| tree | 5683d789f5b9b57d0006dbfbb0f7d03782deca10 /arch/arm/dts/Makefile | |
| parent | cdeb7b8f984e6d9bcdc5a6fdda6107af156d47bf (diff) | |
| parent | 908daf86f96a44176ecd1e04f1ec71e143aa45f5 (diff) | |
| download | u-boot-47754334b164eae4fde538c406ff3678dfb05042.zip u-boot-47754334b164eae4fde538c406ff3678dfb05042.tar.gz u-boot-47754334b164eae4fde538c406ff3678dfb05042.tar.bz2 | |
Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.01-v2
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
Diffstat (limited to 'arch/arm/dts/Makefile')
| -rw-r--r-- | arch/arm/dts/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d8b0a91..bd97604 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -279,6 +279,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ |