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| author | Tom Rini <trini@konsulko.com> | 2017-06-19 08:08:40 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-06-19 08:08:40 -0400 |
| commit | ebba9d1daf7745483c8078bdae18875a84df5bc1 (patch) | |
| tree | 81efc202d2998ed07ef5bdf1d1b16e4280f74501 /arch/arm/cpu | |
| parent | b9f7d8817424bb328d5eac9b16196a1189b8b6f5 (diff) | |
| parent | 2b1a33213e810f43f9d7e33b9d8db99e1b80a1c0 (diff) | |
| download | u-boot-ebba9d1daf7745483c8078bdae18875a84df5bc1.zip u-boot-ebba9d1daf7745483c8078bdae18875a84df5bc1.tar.gz u-boot-ebba9d1daf7745483c8078bdae18875a84df5bc1.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci.c | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index b3a34de..18da9cb 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -118,6 +118,23 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, } } +#ifdef CONFIG_MACH_SUN8I_R40 +/* secondary core entry address is programmed differently on R40 */ +static void __secure sunxi_set_entry_address(void *entry) +{ + writel((u32)entry, + SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); +} +#else +static void __secure sunxi_set_entry_address(void *entry) +{ + struct sunxi_cpucfg_reg *cpucfg = + (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; + + writel((u32)entry, &cpucfg->priv0); +} +#endif + #ifdef CONFIG_MACH_SUN7I /* sun7i (A20) is different from other single cluster SoCs */ static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on) @@ -236,13 +253,7 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc) psci_save_target_pc(cpu, pc); /* Set secondary core power on PC */ -#ifdef CONFIG_MACH_SUN8I_R40 - /* secondary core entry address is programmed differently */ - writel((u32)&psci_cpu_entry, - SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); -#else - writel((u32)&psci_cpu_entry, &cpucfg->priv0); -#endif + sunxi_set_entry_address(&psci_cpu_entry); /* Assert reset on target CPU */ writel(0, &cpucfg->cpu[cpu].rst); |