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author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2018-04-25 14:25:42 +0800 |
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committer | York Sun <york.sun@nxp.com> | 2018-05-09 09:17:51 -0500 |
commit | 8b40f22900f3618ab1b83d15d078ab6f75c7c800 (patch) | |
tree | 2a1365c9ff63d5cdcaae795132ab96116fe3911b /arch/arm/cpu/armv8/fsl-layerscape/soc.c | |
parent | 945fad57be827482091c6d39443d51052c7a8d7d (diff) | |
download | u-boot-8b40f22900f3618ab1b83d15d078ab6f75c7c800.zip u-boot-8b40f22900f3618ab1b83d15d078ab6f75c7c800.tar.gz u-boot-8b40f22900f3618ab1b83d15d078ab6f75c7c800.tar.bz2 |
armv8/fsl-lsch2: make the workaround for PIN MUX erratum A010539 robust
Mask HRESET_B after cleared the the RCW_SRC, because in the workaround
we override the RCW_SRC and if HRESET_B is issued after the override
then SoC cannot find valid RCW as the RCW_SRC was overwritten and
result in hang. So we need to mask HRESET_B in case user asserts it,
and the PORESET_B should be asserted which leads to resampling of
cfg_rcw_src pins and loading of correct RCW_SRC.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06fdd17..bfd6639 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -517,6 +517,7 @@ static void erratum_a010539(void) porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); + out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif } |