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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-07 19:18:44 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-22 20:59:22 +0200 |
| commit | d1c3d8bdfa41a7002bc9c9c0fe8cf7b41d573c0e (patch) | |
| tree | 4060adc5d2ada1f03064cdde537f8d0a6939e8c2 /README | |
| parent | 32f3179ae602971beb29e9d1981e77f9006a2c53 (diff) | |
| download | u-boot-d1c3d8bdfa41a7002bc9c9c0fe8cf7b41d573c0e.zip u-boot-d1c3d8bdfa41a7002bc9c9c0fe8cf7b41d573c0e.tar.gz u-boot-d1c3d8bdfa41a7002bc9c9c0fe8cf7b41d573c0e.tar.bz2 | |
MIPS: start.S: make boot config at offset 0x10 configurable
Some MIPS systems store some board-specific boot configuration
in the U-Boot binary at offset 0x10. This is used by Malta boards
and by Lantiq/Intel SoC's when booting from parallel NOR flash.
Convert the hard-coded values to Kconfig options to remove such
board-specific stuff out of the generic start.S code. This also
deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 0 insertions, 5 deletions
@@ -542,11 +542,6 @@ The following options need to be configured: CONF_CM_CACHABLE_CUW CONF_CM_CACHABLE_ACCELERATED - CONFIG_SYS_XWAY_EBU_BOOTCFG - - Special option for Lantiq XWAY SoCs for booting from NOR flash. - See also arch/mips/cpu/mips32/start.S. - CONFIG_XWAY_SWAP_BYTES Enable compilation of tools/xway-swap-bytes needed for Lantiq |