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| author | Tom Rini <trini@konsulko.com> | 2022-03-30 18:07:35 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-04-08 10:46:22 -0400 |
| commit | 6751b700556fea94b30e19b7cc1abb509b49a5bc (patch) | |
| tree | e7e028d4c1629df36be38b1b168fb58805aabebe /README | |
| parent | 001a56b0082a02e82b433eed362aa37ea4255fdb (diff) | |
| download | u-boot-6751b700556fea94b30e19b7cc1abb509b49a5bc.zip u-boot-6751b700556fea94b30e19b7cc1abb509b49a5bc.tar.gz u-boot-6751b700556fea94b30e19b7cc1abb509b49a5bc.tar.bz2 | |
arm: fsl-layerscape: Migrate more DP-DDR options to Kconfig
Based on current usage, migrate a number of DP-DDR related options to
Kconfig.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 0 insertions, 3 deletions
@@ -487,9 +487,6 @@ The following options need to be configured: CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS Number of controllers used for other than main memory. - CONFIG_SYS_FSL_HAS_DP_DDR - Defines the SoC has DP-DDR used for DPAA. - CONFIG_SYS_FSL_SEC_BE Defines the SEC controller register space as Big Endian |