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authorAshish Kumar <Ashish.Kumar@nxp.com>2017-08-18 10:54:36 +0530
committerYork Sun <york.sun@nxp.com>2017-09-11 07:55:36 -0700
commitc055cee1951a01a3306f54f20bcfb85adf28721a (patch)
treeb59727a8075cfc4b7375f3686b38581f9de9d466 /README
parentc8bc3c0c9ff7ce649b2af1416919b50ecf504874 (diff)
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armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs in LSCH3 family may have differnt interconnect. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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@@ -322,6 +322,10 @@ build a config tool - later.
Defined For SoC that has cache coherent interconnect
CCN-400
+ CONFIG_SYS_FSL_HAS_CCN504
+
+ Defined for SoC that has cache coherent interconnect CCN-504
+
The following options need to be configured:
- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.