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| author | Michal Simek <michal.simek@xilinx.com> | 2021-10-15 15:17:29 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2022-03-30 14:50:47 +0200 |
| commit | fb92cc2c17724d66a32f7a033608a1bd2176a478 (patch) | |
| tree | d1119d0f13dde85e40980d4ae94c1620dc63714e /MAINTAINERS | |
| parent | dcbdd24259beaff903e7ffffde646a3c5bd756ac (diff) | |
| download | u-boot-fb92cc2c17724d66a32f7a033608a1bd2176a478.zip u-boot-fb92cc2c17724d66a32f7a033608a1bd2176a478.tar.gz u-boot-fb92cc2c17724d66a32f7a033608a1bd2176a478.tar.bz2 | |
pwm: Add driver for cadence TTC
TTC has three modes of operations. Timer, PWM and input counters.
There is already driver for timer under CADENCE_TTC_TIMER which is used for
ZynqMP R5 configuration.
This driver is targeting PWM which is for example configuration which can
be used for fan control.
The driver has been tested on Xilinx Kria SOM platform where fan is
connected to one PL pin. When TTC output is connected via EMIO to PL pin
TTC pwm can be configured and tested for example like this:
pwm config 0 0 10000 1200
pwm enable 0 0
pwm config 0 0 10000 1400
pwm config 0 0 10000 1600
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/915a662ddb88f7a958ca1f307e8fea59af9d7feb.1634303847.git.michal.simek@xilinx.com
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 74d5263..36044f6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -655,6 +655,7 @@ F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c F: drivers/phy/phy-zynqmp.c F: drivers/power/domain/zynqmp-power-domain.c +F: drivers/pwm/pwm-cadence-ttc.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c |