diff options
author | Tom Rini <trini@konsulko.com> | 2024-07-18 07:49:14 -0600 |
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committer | Tom Rini <trini@konsulko.com> | 2024-07-18 07:49:14 -0600 |
commit | dce89b3bfc5ed2d2f5439474f7edda1a3b085094 (patch) | |
tree | 2d3fdebd6e4f5b737604be4b15076e2c2ccd1e4e | |
parent | 84ab75fb56337a7c186044850d3f6555bc644df1 (diff) | |
parent | e8b3f6c1018e1401bcc697a8aed8120061e4f189 (diff) | |
download | u-boot-dce89b3bfc5ed2d2f5439474f7edda1a3b085094.zip u-boot-dce89b3bfc5ed2d2f5439474f7edda1a3b085094.tar.gz u-boot-dce89b3bfc5ed2d2f5439474f7edda1a3b085094.tar.bz2 |
Merge tag 'u-boot-rockchip-20240718' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add boards:
rk3328: Radxa ROCK Pi E v3;
rk3588s: FriendlyElec NanoPi R6C/S;
- Remove board: Theobroma Systems RK3368 Lion;
- Add rk3588 pcie support;
- Misc updates for board and config;
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/2163
54 files changed, 605 insertions, 921 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4a4d5be..7265e55 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -83,7 +83,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ - rk3368-lion-haikou.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \ diff --git a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi new file mode 100644 index 0000000..39bb66c --- /dev/null +++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Radxa + */ + +#include "rk3328-u-boot.dtsi" + +/ { + smbios { + compatible = "u-boot,sysinfo-smbios"; + + smbios { + system { + manufacturer = "radxa"; + product = "rock-pi-e_rk3328"; + }; + + baseboard { + manufacturer = "radxa"; + product = "rock-pi-e_rk3328"; + }; + + chassis { + manufacturer = "radxa"; + product = "rock-pi-e_rk3328"; + }; + }; + }; +}; + +&u2phy_host { + phy-supply = <&vcc_host_5v>; +}; + +&vcc_host_5v { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; +}; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi index d314bfa..8e82f6a 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -1,43 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2020 Radxa - */ -#include "rk3328-u-boot.dtsi" +#include "rk3328-rock-pi-e-base-u-boot.dtsi" #include "rk3328-sdram-ddr3-666.dtsi" - -/ { - smbios { - compatible = "u-boot,sysinfo-smbios"; - - smbios { - system { - manufacturer = "radxa"; - product = "rock-pi-e_rk3328"; - }; - - baseboard { - manufacturer = "radxa"; - product = "rock-pi-e_rk3328"; - }; - - chassis { - manufacturer = "radxa"; - product = "rock-pi-e_rk3328"; - }; - }; - }; -}; - -&u2phy_host { - phy-supply = <&vcc_host_5v>; -}; - -&vcc_host_5v { - /delete-property/ regulator-always-on; - /delete-property/ regulator-boot-on; -}; - -&vcc_sd { - bootph-pre-ram; -}; diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi new file mode 100644 index 0000000..4d89ae5 --- /dev/null +++ b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3328-rock-pi-e-base-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" diff --git a/arch/arm/dts/rk3328-rock-pi-e-v3.dts b/arch/arm/dts/rk3328-rock-pi-e-v3.dts new file mode 100644 index 0000000..f1c1c36 --- /dev/null +++ b/arch/arm/dts/rk3328-rock-pi-e-v3.dts @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3328-rock-pi-e.dts" diff --git a/arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi b/arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi deleted file mode 100644 index a3c2b70..0000000 --- a/arch/arm/dts/rk3368-lion-haikou-u-boot.dtsi +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include "rk3368-u-boot.dtsi" - -/ { - config { - u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ - u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - u-boot,spl-boot-order = &emmc, &sdmmc; - }; - - smbios { - compatible = "u-boot,sysinfo-smbios"; - - smbios { - system { - manufacturer = "rockchip"; - product = "sheep_rk3368"; - }; - - baseboard { - manufacturer = "rockchip"; - product = "sheep_rk3368"; - }; - - chassis { - manufacturer = "rockchip"; - product = "sheep_rk3368"; - }; - }; - }; -}; - -&gpio2 { - bootph-all; -}; - -&pinctrl { - bootph-all; -}; - -&service_msch { - bootph-all; -}; - -&dmc { - bootph-all; - - /* - * Validation of throughput using SPEC2000 shows the following - * relative performance for the different memory schedules: - * - CBDR: 30.1 - * - CBRD: 29.8 - * - CRBD: 29.9 - * Note that the best performance for any given application workload - * may vary from the default configured here (e.g. 164.gzip is fastest - * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD). - * - * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for - * details on the 'rockchip,memory-schedule' property and how it - * affects the physical-address to device-address mapping. - */ - rockchip,memory-schedule = <DMC_MSCH_CBDR>; - rockchip,ddr-frequency = <800000000>; - rockchip,ddr-speed-bin = <DDR3_1600K>; - - status = "okay"; -}; - -&pmugrf { - bootph-all; -}; - -&sgrf { - bootph-all; -}; - -&cru { - bootph-all; -}; - -&grf { - bootph-all; -}; - -&uart0 { - bootph-all; -}; - -&emmc { - bootph-pre-ram; -}; - -&sdmmc { - bootph-pre-ram; -}; - -&spi1 { - bootph-pre-ram; - - spiflash: w25q32dw@0 { - bootph-pre-ram; - }; -}; - -&timer0 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - - diff --git a/arch/arm/dts/rk3368-lion-haikou.dts b/arch/arm/dts/rk3368-lion-haikou.dts deleted file mode 100644 index cae01d3..0000000 --- a/arch/arm/dts/rk3368-lion-haikou.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "rk3368-lion.dtsi" - -/ { - model = "Theobroma Systems RK3368-uQ7 Baseboard"; - compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368"; - - aliases { - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2cmux2 { - i2c@0 { - eeprom: eeprom@50 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x50>; - }; - }; - }; - - leds { - pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>; - - sd_card_led: led-3 { - label = "sd_card_led"; - gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_baseboard: vcc3v3-baseboard { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <25000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - rockchip,default-sample-phase = <90>; - vmmc-supply = <&vcc3v3_baseboard>; - status = "okay"; -}; - -&spi2 { - cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart1 { - /* alternate function of GPIO5/6 */ - status = "disabled"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&haikou_pin_hog>; - - hog { - haikou_pin_hog: haikou-pin-hog { - rockchip,pins = - /* LID_BTN */ - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - /* BATLOW# */ - <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, - /* SLP_BTN# */ - <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - /* BIOS_DISABLE# */ - <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - sd_card_led_pin: sd-card-led-pin { - rockchip,pins = - <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_cd_pin: sdmmc-cd-pin { - rockchip,pins = - <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = - <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3368-lion.dtsi b/arch/arm/dts/rk3368-lion.dtsi deleted file mode 100644 index bcd7977..0000000 --- a/arch/arm/dts/rk3368-lion.dtsi +++ /dev/null @@ -1,318 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "rk3368.dtsi" - -/ { - aliases { - mmc0 = &emmc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - ext_gmac: gmac-clk { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - i2cmux1 { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c1>; - mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - - /* Q7_GPO_I2C */ - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* Q7_SMB */ - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - i2cmux2 { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c2>; - mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - - /* Q7_LVDS_BLC_I2C */ - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; - }; - - /* Q7_GP2_I2C */ - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&module_led_pins>; - - module_led1: led-1 { - label = "module_led1"; - gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - - module_led2: led-2 { - label = "module_led2"; - gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - clock-frequency = <150000000>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc33_io>; - vqmmc-supply = <&vcc18_io>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc33_io>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; - tx_delay = <0x10>; - rx_delay = <0x10>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>; - clock-output-names = "xin32k", "rk808-clkout2"; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>; - rockchip,system-power-controller; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_sys>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: DCDC_REG2 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - }; - - vcc33_io: DCDC_REG4 { - regulator-name = "vcc33_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc33_video: LDO_REG2 { - regulator-name = "vcc33_video"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd10_pll: LDO_REG3 { - regulator-name = "vdd10_pll"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc18_io: LDO_REG4 { - regulator-name = "vcc18_io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - vdd10_video: LDO_REG6 { - regulator-name = "vdd10_video"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc18_video: LDO_REG8 { - regulator-name = "vcc18_video"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&pinctrl { - leds { - module_led_pins: module-led-pins { - rockchip,pins = - <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, - <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_sleep: pmic-sleep { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; -}; - -&spi1 { - status = "okay"; - - norflash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index b6b4327..2bec139 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -145,6 +145,11 @@ bootph-some-ram; }; +&spi1 { + bootph-pre-ram; + bootph-some-ram; +}; + &spi1_clk { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi b/arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi new file mode 100644 index 0000000..853ed58 --- /dev/null +++ b/arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi b/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi new file mode 100644 index 0000000..853ed58 --- /dev/null +++ b/arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 9778790..c3259b8 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -17,6 +17,8 @@ # include <asm/arch-rockchip/cru_rk3399.h> #elif defined(CONFIG_ROCKCHIP_RK3568) #include <asm/arch-rockchip/cru_rk3568.h> +#elif defined(CONFIG_ROCKCHIP_RK3588) +#include <asm/arch-rockchip/cru_rk3588.h> #endif /* CRU_GLB_RST_ST */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index a0e54d3..dad4848 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -92,6 +92,8 @@ struct rk3588_cru { unsigned int pmuclkgate_con[9]; /* Address Offset: 0x0100 */ }; +#define rockchip_cru rk3588_cru + check_member(rk3588_cru, mode_con00, 0x280); check_member(rk3588_cru, pmuclksel_con[1], 0x30304); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 14b3ab1..fc1b638 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -16,6 +16,8 @@ config ROCKCHIP_PX30 select DEBUG_UART_BOARD_INIT imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN help The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -167,6 +169,7 @@ config ROCKCHIP_RK3308 imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R + imply OF_LIBFDT_OVERLAY imply OF_UPSTREAM imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD @@ -197,6 +200,7 @@ config ROCKCHIP_RK3328 imply ARMV8_SET_SMPEN imply MISC imply MISC_INIT_R + imply OF_LIBFDT_OVERLAY imply OF_LIVE imply OF_UPSTREAM imply PRE_CONSOLE_BUFFER diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c b/arch/arm/mach-rockchip/px30/syscon_px30.c index c9de574..893a523 100644 --- a/arch/arm/mach-rockchip/px30/syscon_px30.c +++ b/arch/arm/mach-rockchip/px30/syscon_px30.c @@ -18,6 +18,9 @@ static const struct udevice_id px30_syscon_ids[] = { U_BOOT_DRIVER(syscon_px30) = { .id = UCLASS_SYSCON, .name = "px30_syscon", +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif .of_match = px30_syscon_ids, }; diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 3de6951..a7be30b 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -3,27 +3,6 @@ if ROCKCHIP_RK3368 choice prompt "RK3368 board" -config TARGET_LION_RK3368 - bool "Theobroma Systems RK3368-uQ7 (Lion) module" - select ARCH_EARLY_INIT_R - help - The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm, - MXM-230 connector) system-on-module designed by Theobroma - Systems for industrial applications. - - It provides the following features: - - 8x Cortex-A53 (in 2 clusters of 4 cores each) - - (on-module) up to 4GB of DDR3 memory - - (on-module) SPI-NOR flash - - (on-module) eMMC - - Gigabit Ethernet (with an on-module KSZ9031 PHY) - - USB - - HDMI - - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group) - - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...) - - on-module STM32 providing CAN, RTC and fan-control - - (optional on-module) EAL4+-certified security module - config TARGET_SHEEP bool "Sheep board" help @@ -62,7 +41,6 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" source "board/rockchip/evb_px5/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 9a35c7d..e751d64 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -78,6 +78,30 @@ config TARGET_NANOPCT6_RK3588 Power: 5.5*2.1mm DC Jack, 12VDC input Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case) +config TARGET_NANOPI_R6C_RK3588S + bool "FriendlyElec NanoPi R6C" + select BOARD_LATE_INIT + help + The NanoPi R6C is a SBC by FriendlyElec based on the Rockchip + RK3588s. + It comes with 4GB or 8GB of RAM, a microSD card slot, optional 32GB + eMMC storage, one M.2 M-Key connector, one RTL8211F 1GbE and one + RTL8125 2.5GbE Ethernet port, one USB 2.0 Type-A and one USB 3.0 + Type-A port, a HDMI port, a 30-pin GPIO header as well as some + buttons and LEDs. + +config TARGET_NANOPI_R6S_RK3588S + bool "FriendlyElec NanoPi R6S" + select BOARD_LATE_INIT + help + The NanoPi R6S is a SBC by FriendlyElec based on the Rockchip + RK3588s. + It comes with 4GB or 8GB of RAM, a microSD card slot, 32GB eMMC + storage, one RTL8211F 1GbE and two RTL8125 2.5GbE Ethernet ports, + one USB 2.0 Type-A and one USB 3.0 Type-A port, a HDMI port, a + 12-pin GPIO FPC connector, a fan connector, IR receiver as well + as some buttons and LEDs. + config TARGET_NOVA_RK3588 bool "Indiedroid Nova RK3588" select BOARD_LATE_INIT @@ -288,6 +312,8 @@ config TEXT_BASE source "board/armsom/sige7-rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" +source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" +source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" source "board/indiedroid/nova/Kconfig" source "board/pine64/quartzpro64-rk3588/Kconfig" source "board/turing/turing-rk1-rk3588/Kconfig" diff --git a/board/friendlyelec/nanopi-r6c-rk3588s/Kconfig b/board/friendlyelec/nanopi-r6c-rk3588s/Kconfig new file mode 100644 index 0000000..2d8acbf --- /dev/null +++ b/board/friendlyelec/nanopi-r6c-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NANOPI_R6C_RK3588S + +config SYS_BOARD + default "nanopi-r6c-rk3588s" + +config SYS_VENDOR + default "friendlyelec" + +config SYS_CONFIG_NAME + default "nanopi-r6c-rk3588s" + +endif diff --git a/board/friendlyelec/nanopi-r6c-rk3588s/MAINTAINERS b/board/friendlyelec/nanopi-r6c-rk3588s/MAINTAINERS new file mode 100644 index 0000000..18d0bd1 --- /dev/null +++ b/board/friendlyelec/nanopi-r6c-rk3588s/MAINTAINERS @@ -0,0 +1,7 @@ +NANOPI-R6C +M: Sebastian Kropatsch <seb-dev@mail.de> +S: Maintained +F: arch/arm/dts/rk3588s-nanopi-r6c-u-boot.dtsi +F: board/friendlyelec/nanopi-r6c-rk3588s +F: configs/nanopi-r6c-rk3588s_defconfig +F: include/configs/nanopi-r6c-rk3588s.h diff --git a/board/friendlyelec/nanopi-r6s-rk3588s/Kconfig b/board/friendlyelec/nanopi-r6s-rk3588s/Kconfig new file mode 100644 index 0000000..4d57981 --- /dev/null +++ b/board/friendlyelec/nanopi-r6s-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NANOPI_R6S_RK3588S + +config SYS_BOARD + default "nanopi-r6s-rk3588s" + +config SYS_VENDOR + default "friendlyelec" + +config SYS_CONFIG_NAME + default "nanopi-r6s-rk3588s" + +endif diff --git a/board/friendlyelec/nanopi-r6s-rk3588s/MAINTAINERS b/board/friendlyelec/nanopi-r6s-rk3588s/MAINTAINERS new file mode 100644 index 0000000..76288b4 --- /dev/null +++ b/board/friendlyelec/nanopi-r6s-rk3588s/MAINTAINERS @@ -0,0 +1,7 @@ +NANOPI-R6S +M: Sebastian Kropatsch <seb-dev@mail.de> +S: Maintained +F: arch/arm/dts/rk3588s-nanopi-r6s-u-boot.dtsi +F: board/friendlyelec/nanopi-r6s-rk3588s +F: configs/nanopi-r6s-rk3588s_defconfig +F: include/configs/nanopi-r6s-rk3588s.h diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 675b72d..8f619e5 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -64,5 +64,5 @@ M: Banglang Huang <banglang.huang@foxmail.com> R: Jonas Karlman <jonas@kwiboo.se> S: Maintained F: configs/rock-pi-e-rk3328_defconfig -F: arch/arm/dts/rk3328-rock-pi-e.dts -F: arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +F: configs/rock-pi-e-v3-rk3328_defconfig +F: arch/arm/dts/rk3328-rock-pi-e* diff --git a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS index ab7051b..370d0a1 100644 --- a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS +++ b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS @@ -10,4 +10,4 @@ F: include/configs/jaguar_rk3588.h F: arch/arm/dts/rk3588-jaguar* F: configs/jaguar-rk3588_defconfig W: https://embedded.cherry.de/product/jaguar-sbc-rk3588/ -T: git git://git.embedded.cherry.de/jaguar-u-boot.git +T: git https://git.embedded.cherry.de/jaguar-u-boot.git diff --git a/board/theobroma-systems/lion_rk3368/Kconfig b/board/theobroma-systems/lion_rk3368/Kconfig deleted file mode 100644 index 537a2e7..0000000 --- a/board/theobroma-systems/lion_rk3368/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_LION_RK3368 - -config SYS_BOARD - default "lion_rk3368" - -config SYS_VENDOR - default "theobroma-systems" - -config SYS_CONFIG_NAME - default "lion_rk3368" - -config ENV_SIZE - default 0x2000 - -config ENV_OFFSET - default 0x3c000 if ENV_IS_IN_SPI_FLASH - -endif diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS b/board/theobroma-systems/lion_rk3368/MAINTAINERS deleted file mode 100644 index ed35fee..0000000 --- a/board/theobroma-systems/lion_rk3368/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -LION-RK3368 (RK3368-uQ7 system-on-module) -M: Quentin Schulz <quentin.schulz@cherry.de> -M: Klaus Goger <klaus.goger@cherry.de> -S: Maintained -F: board/theobroma-systems/lion_rk3368 -F: include/configs/lion_rk3368.h -F: arch/arm/dts/rk3368-lion.dts -F: configs/lion-rk3368_defconfig -W: https://www.theobroma-systems.com/rk3368-uq7/tech-specs -T: git git://git.theobroma-systems.com/lion-u-boot.git diff --git a/board/theobroma-systems/lion_rk3368/README b/board/theobroma-systems/lion_rk3368/README deleted file mode 100644 index 7488b18..0000000 --- a/board/theobroma-systems/lion_rk3368/README +++ /dev/null @@ -1,78 +0,0 @@ -Here is the step-by-step to boot to U-Boot on RK3368-uQ7 - -Get the Source and build ATF -============================ - - > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git - > cd arm-trusted-firmware - > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3368 bl31 - > cp build/rk3368/release/bl31.bin ../u-boot/bl31-rk3368.bin - -Configure U-Boot -================ - - > cd ../u-boot - > make lion-rk3368_defconfig - -Build the TPL/SPL stage -======================= - - > make CROSS_COMPILE=aarch64-unknown-elf- - -Build the full U-Boot and a FIT image including the ATF -======================================================= - - > make CROSS_COMPILE=aarch64-unknown-elf- u-boot.itb - -Flash the image -=============== - -Copy the SPL to offset 32k and the FIT image containing the payloads -(U-Boot proper, ATF, devicetree) to offset 256k card. - -SD-Card -------- - - > dd if=idbloader.img of=/dev/sdb seek=64 - > dd if=u-boot.itb of=/dev/sdb seek=512 - -eMMC ----- - -rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with -help of the Rockchip loader binary. - - > git clone https://github.com/rockchip-linux/rkdeveloptool - > cd rkdeveloptool - > autoreconf -i && && ./configure && make - > git clone https://github.com/rockchip-linux/rkbin.git - > ./rkdeveloptool db rkbin/rk33/rk3368_loader_v2.00.256.bin - > ./rkdeveloptool wl 64 ../spl.img - > ./rkdeveloptool wl 512 ../u-boot.itb - - -If everything went according to plan, you should see the following -output on UART0: - -<debug_uart> U-Boot TPL board init -Trying to boot from BOOTROM -Returning to boot ROM... -Trying to boot from MMC1 -NOTICE: BL31: v1.3(release):v1.2-1320-gbf43a443 -NOTICE: BL31: Built : 18:04:47, Jul 5 2017 - - -U-Boot 2017.07-00158-g2395e99858 (Jul 18 2017 - 21:03:31 +0200) - -Model: Theobroma Systems RK3368-uQ7 SoM -DRAM: 2 GiB -MMC: dwmmc@ff0c0000: 1, dwmmc@ff0f0000: 0 -Using default environment - -In: serial@ff180000 -Out: serial@ff180000 -Err: serial@ff180000 -Net: -Warning: ethernet@ff290000 (eth0) using random MAC address - d2:69:35:7e:d0:1e -eth0: ethernet@ff290000 -Hit any key to stop autoboot: 2 diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS index 2536e34..1a5b78b 100644 --- a/board/theobroma-systems/puma_rk3399/MAINTAINERS +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -9,4 +9,4 @@ F: include/configs/puma_rk3399.h F: arch/arm/dts/rk3399-puma* F: configs/puma-rk3399_defconfig W: https://embedded.cherry.de/product/puma-som-rk3399-q7/ -T: git git://git.embedded.cherry.de/puma-u-boot.git +T: git https://git.embedded.cherry.de/puma-u-boot.git diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS index 2aff91f..4d4544a 100644 --- a/board/theobroma-systems/ringneck_px30/MAINTAINERS +++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS @@ -9,4 +9,4 @@ F: include/configs/ringneck_px30.h F: arch/arm/dts/px30-ringneck* F: configs/ringneck-px30_defconfig W: https://embedded.cherry.de/product/ringneck-som-px30-uq7/ -T: git git://git.embedded.cherry.de/ringneck-u-boot.git +T: git https://git.embedded.cherry.de/ringneck-u-boot.git diff --git a/board/theobroma-systems/tiger_rk3588/MAINTAINERS b/board/theobroma-systems/tiger_rk3588/MAINTAINERS index e5aab4b..a951356 100644 --- a/board/theobroma-systems/tiger_rk3588/MAINTAINERS +++ b/board/theobroma-systems/tiger_rk3588/MAINTAINERS @@ -10,4 +10,4 @@ F: include/configs/tiger_rk3588.h F: arch/arm/dts/rk3588-tiger* F: configs/tiger-rk3588_defconfig W: https://embedded.cherry.de/product/tiger-som-rk3588-q7/ -T: git git://git.embedded.cherry.de/tiger-u-boot.git +T: git https://git.embedded.cherry.de/tiger-u-boot.git diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index f4c2ea1..6d090db 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-evb" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y CONFIG_TARGET_EVB_RK3308=y diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 36bf34d..1800646 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -13,6 +13,7 @@ CONFIG_TARGET_JAGUAR_RK3588=y CONFIG_DEBUG_UART_BASE=0xfeb50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -40,6 +41,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -88,7 +90,10 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y diff --git a/configs/nanopi-r6c-rk3588s_defconfig b/configs/nanopi-r6c-rk3588s_defconfig new file mode 100644 index 0000000..f8d2d67 --- /dev/null +++ b/configs/nanopi-r6c-rk3588s_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-nanopi-r6c" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_NANOPI_R6C_RK3588S=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-nanopi-r6c.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_SPI_FLASH is not set +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r6s-rk3588s_defconfig b/configs/nanopi-r6s-rk3588s_defconfig new file mode 100644 index 0000000..f7b3646 --- /dev/null +++ b/configs/nanopi-r6s-rk3588s_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-nanopi-r6s" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_NANOPI_R6S_RK3588S=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-nanopi-r6s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_SPI_FLASH is not set +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 5319239..9e5499a 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -56,6 +56,8 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y @@ -69,6 +71,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ANEG_TIMEOUT=30000 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index 2320479..52a4c97 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -15,11 +15,12 @@ CONFIG_DEBUG_UART_BASE=0xFF030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y -# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTD_FULL=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -42,6 +43,7 @@ CONFIG_SPL_ATF=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set +CONFIG_CMD_BIND=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -49,7 +51,6 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -73,14 +74,13 @@ CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_BUF_ADDR=0x800800 -CONFIG_FASTBOOT_BUF_SIZE=0x04000000 CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y @@ -112,10 +112,9 @@ CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y +# CONFIG_RSA is not set CONFIG_LZO=y CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 862ea43..b1b59d9 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -4,7 +4,6 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-roc-cc" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y CONFIG_TARGET_ROC_RK3308_CC=y diff --git a/configs/lion-rk3368_defconfig b/configs/rock-pi-e-v3-rk3328_defconfig index 868eeaf..4c6cc63 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/rock-pi-e-v3-rk3328_defconfig @@ -2,66 +2,48 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou" -CONFIG_SPL_TEXT_BASE=0x00000000 -CONFIG_ROCKCHIP_RK3368=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x188000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SPL_BSS_MAX_SIZE=0x20000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xFF180000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e-v3" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_BOOTSTAGE=y -CONFIG_SPL_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y -CONFIG_BOOTSTAGE_FDT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-lion-haikou.dtb" +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 +CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y -CONFIG_TPL=y -CONFIG_TPL_SYS_MALLOC_SIMPLE=y -CONFIG_TPL_DRIVERS_MISC=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_MTDPARTS=y CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y -CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent" +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_TPL_REGMAP=y @@ -70,41 +52,46 @@ CONFIG_SPL_SYSCON=y CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_TPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_ANEG_TIMEOUT=8000 -CONFIG_PHY_MSCC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y -CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550_MEM32=y -CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_TINY_MEMSET=y -CONFIG_LZO=y +CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index c15ba3d..e450a06 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-pi-s" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y CONFIG_TARGET_EVB_RK3308=y diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig index 8fcdd06..8eb1027 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -14,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0xfeb50000 CONFIG_DEBUG_UART_CLOCK=24000000 # CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -41,6 +42,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -89,6 +91,8 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_PHY_ROCKCHIP_USBDP=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index eaf7167..bedc52e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -72,7 +72,6 @@ List of mainline supported Rockchip boards: - GeekBox (geekbox) - PX5 EVB (evb-px5) - Rockchip Sheep (sheep-rk3368) - - Theobroma Systems RK3368-uQ7 SoM - Lion (lion-rk3368) * rk3399 - 96boards RK3399 Ficus (ficus-rk3399) - 96boards Rock960 (rock960-rk3399) @@ -124,6 +123,8 @@ List of mainline supported Rockchip boards: - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) + - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s) + - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s) - Generic RK3588S/RK3588 (generic-rk3588) - Indiedroid Nova (nova-rk3588s) - Pine64 QuartzPro64 (quartzpro64-rk3588) diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c index 04d4d07..cf4f7c3 100644 --- a/drivers/misc/rockchip-io-domain.c +++ b/drivers/misc/rockchip-io-domain.c @@ -27,6 +27,10 @@ #define MAX_VOLTAGE_1_8 1980000 #define MAX_VOLTAGE_3_3 3600000 +#define PX30_IO_VSEL 0x180 +#define PX30_IO_VSEL_VCCIO6_SRC BIT(0) +#define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1 + #define RK3328_SOC_CON4 0x410 #define RK3328_SOC_CON4_VCCIO2 BIT(7) #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 @@ -99,6 +103,22 @@ static int rockchip_iodomain_write(struct regmap *grf, uint offset, int idx, int return regmap_write(grf, offset, val); } +static int px30_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) +{ + int ret = rockchip_iodomain_write(grf, offset, idx, uV); + + if (!ret && idx == PX30_IO_VSEL_VCCIO6_SUPPLY_NUM) { + /* + * set vccio6 iodomain to also use this framework + * instead of a special gpio. + */ + u32 val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16); + ret = regmap_write(grf, PX30_IO_VSEL, val); + } + + return ret; +} + static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) { int ret = rockchip_iodomain_write(grf, offset, idx, uV); @@ -131,6 +151,44 @@ static int rk3399_pmu_iodomain_write(struct regmap *grf, uint offset, int idx, i return ret; } +static const struct rockchip_iodomain_soc_data soc_data_px30 = { + .grf_offset = 0x180, + .supply_names = { + NULL, + "vccio6-supply", + "vccio1-supply", + "vccio2-supply", + "vccio3-supply", + "vccio4-supply", + "vccio5-supply", + "vccio-oscgpi-supply", + }, + .write = px30_iodomain_write, +}; + +static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = { + .grf_offset = 0x100, + .supply_names = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "pmuio1-supply", + "pmuio2-supply", + }, + .write = rockchip_iodomain_write, +}; + static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { .grf_offset = 0x410, .supply_names = { @@ -191,6 +249,14 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { static const struct udevice_id rockchip_iodomain_ids[] = { { + .compatible = "rockchip,px30-io-voltage-domain", + .data = (ulong)&soc_data_px30, + }, + { + .compatible = "rockchip,px30-pmu-io-voltage-domain", + .data = (ulong)&soc_data_px30_pmu, + }, + { .compatible = "rockchip,rk3328-io-voltage-domain", .data = (ulong)&soc_data_rk3328, }, diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 3bb1a25..7459779 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -432,8 +432,8 @@ static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, inno_write(inno, reg, tmp); } -#define inno_poll(reg, val, cond, sleep_us, timeout_us) \ - readl_poll_sleep_timeout((reg) * 4, val, cond, sleep_us, timeout_us) +#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ + readl_poll_sleep_timeout((inno)->regs + ((reg) * 4), val, cond, sleep_us, timeout_us) static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, unsigned long rate) @@ -575,7 +575,7 @@ inno_hdmi_phy_rk3328_clk_set_rate(struct phy *phy, inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); /* Wait for Pre-PLL lock */ - ret = inno_poll(0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, + ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, 1000, 10000); if (ret) { dev_err(phy->dev, "Pre-PLL locking failed\n"); @@ -674,7 +674,7 @@ inno_hdmi_phy_rk3328_power_on(struct phy *phy, RK3328_TMDS_DRIVER_ENABLE); /* Wait for post PLL lock */ - ret = inno_poll(0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS, + ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS, 1000, 10000); if (ret) { dev_err(phy->dev, "Post-PLL locking failed\n"); diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 3ad339b..1b85cbc 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -225,7 +225,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a return 0; } -static const struct phy_ops rochchip_combphy_ops = { +static const struct phy_ops rockchip_combphy_ops = { .init = rockchip_combphy_init, .exit = rockchip_combphy_exit, .of_xlate = rockchip_combphy_xlate, @@ -535,7 +535,7 @@ U_BOOT_DRIVER(rockchip_naneng_combphy) = { .name = "naneng-combphy", .id = UCLASS_PHY, .of_match = rockchip_combphy_ids, - .ops = &rochchip_combphy_ops, + .ops = &rockchip_combphy_ops, .probe = rockchip_combphy_probe, .priv_auto = sizeof(struct rockchip_combphy_priv), }; diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index 2737bd8..62b42d1 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -36,6 +36,8 @@ #define RK3588_BIFURCATION_LANE_0_1 BIT(0) #define RK3588_BIFURCATION_LANE_2_3 BIT(1) #define RK3588_LANE_AGGREGATION BIT(2) +#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) +#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16) /** * struct rockchip_p3phy_priv - RK DW PCIe PHY state @@ -108,7 +110,7 @@ static int rockchip_p3phy_rk3588_init(struct phy *phy) { struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); u32 reg = 0; - u8 mode = 0; + u8 mode = RK3588_LANE_AGGREGATION; /* Lane aggregation by default */ int ret; /* Deassert PCIe PMA output clamp mode */ @@ -117,31 +119,23 @@ static int rockchip_p3phy_rk3588_init(struct phy *phy) /* Set bifurcation if needed */ for (int i = 0; i < priv->num_lanes; i++) { - if (!priv->lanes[i]) - mode |= (BIT(i) << 3); - if (priv->lanes[i] > 1) - mode |= (BIT(i) >> 1); - } - - if (!mode) { - reg = RK3588_LANE_AGGREGATION; - } else { - if (mode & (BIT(0) | BIT(1))) - reg |= RK3588_BIFURCATION_LANE_0_1; - - if (mode & (BIT(2) | BIT(3))) - reg |= RK3588_BIFURCATION_LANE_2_3; + mode &= ~RK3588_LANE_AGGREGATION; + if (priv->lanes[i] == 3) + mode |= RK3588_BIFURCATION_LANE_0_1; + if (priv->lanes[i] == 4) + mode |= RK3588_BIFURCATION_LANE_2_3; } + reg = mode; regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, - (0x7 << 16) | reg); + RK3588_PCIE30_PHY_MODE_EN | reg); /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ - reg = (mode & (BIT(6) | BIT(7))) >> 6; + reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3); if (reg) regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, - (reg << 16) | reg); + RK3588_PCIE1LN_SEL_EN | reg); reset_deassert(&priv->p30phy); udelay(1); @@ -164,7 +158,7 @@ static const struct rockchip_p3phy_ops rk3588_ops = { .phy_init = rockchip_p3phy_rk3588_init, }; -static int rochchip_p3phy_init(struct phy *phy) +static int rockchip_p3phy_init(struct phy *phy) { struct rockchip_p3phy_ops *ops = (struct rockchip_p3phy_ops *)dev_get_driver_data(phy->dev); @@ -185,7 +179,7 @@ static int rochchip_p3phy_init(struct phy *phy) return ret; } -static int rochchip_p3phy_exit(struct phy *phy) +static int rockchip_p3phy_exit(struct phy *phy) { struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); @@ -251,9 +245,9 @@ static int rockchip_p3phy_probe(struct udevice *dev) return 0; } -static struct phy_ops rochchip_p3phy_ops = { - .init = rochchip_p3phy_init, - .exit = rochchip_p3phy_exit, +static struct phy_ops rockchip_p3phy_ops = { + .init = rockchip_p3phy_init, + .exit = rockchip_p3phy_exit, }; static const struct udevice_id rockchip_p3phy_of_match[] = { @@ -272,7 +266,7 @@ U_BOOT_DRIVER(rockchip_pcie3phy) = { .name = "rockchip_pcie3phy", .id = UCLASS_PHY, .of_match = rockchip_p3phy_of_match, - .ops = &rochchip_p3phy_ops, + .ops = &rockchip_p3phy_ops, .probe = rockchip_p3phy_probe, .priv_auto = sizeof(struct rockchip_p3phy_priv), }; diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 617bb51..4d5a5ce 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -281,6 +281,8 @@ static int rk8xx_probe(struct udevice *dev) show_variant = bitfield_extract_by_mask(priv->variant, RK8XX_ID_MSK); switch (priv->variant) { case RK808_ID: + /* RK808 ID is 0x0000, so fix show_variant for that PMIC */ + show_variant = 0x808; break; case RK805_ID: case RK816_ID: diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts index 7d7303f..678ed8b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts @@ -72,6 +72,27 @@ }; }; + /* + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE + * clock generator. + * The clock output is gated via the OE pin on the clock generator. + * This is modeled as a fixed-clock plus a gpio-gate-clock. + */ + pcie_refclk_gen: pcie-refclk-gen-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_refclk: pcie-refclk-clock { + compatible = "gpio-gate-clock"; + clocks = <&pcie_refclk_gen>; + #clock-cells = <0>; + enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m0>; + }; + pps { compatible = "pps-gpio"; gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; @@ -353,6 +374,30 @@ status = "okay"; }; +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>; + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */ + vpcie3v3-supply = <&vcc3v3_mdot2>; + status = "okay"; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -371,6 +416,20 @@ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + pcie30x4 { + pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_perstn_m0: pcie30x4-perstn-m0 { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_waken_m0: pcie30x4-waken-m0 { + rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; + }; + }; }; &saradc { diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h deleted file mode 100644 index 0d29e1d..0000000 --- a/include/configs/lion_rk3368.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - */ - -#ifndef __CONFIGS_LION_RK3368_H -#define __CONFIGS_LION_RK3368_H - -#include <configs/rk3368_common.h> - -#define KERNEL_LOAD_ADDR 0x280000 -#define DTB_LOAD_ADDR 0x5600000 -#define INITRD_LOAD_ADDR 0x5bf0000 -/* PHY needs longer aneg time at 1G */ - -#endif diff --git a/include/configs/nanopi-r6c-rk3588s.h b/include/configs/nanopi-r6c-rk3588s.h new file mode 100644 index 0000000..2b57d60 --- /dev/null +++ b/include/configs/nanopi-r6c-rk3588s.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __NANOPI_R6C_RK3588S_H +#define __NANOPI_R6C_RK3588S_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __NANOPI_R6C_RK3588S_H */ diff --git a/include/configs/nanopi-r6s-rk3588s.h b/include/configs/nanopi-r6s-rk3588s.h new file mode 100644 index 0000000..a1b1978 --- /dev/null +++ b/include/configs/nanopi-r6s-rk3588s.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __NANOPI_R6S_RK3588S_H +#define __NANOPI_R6S_RK3588S_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __NANOPI_R6S_RK3588S_H */ diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 861154f..2de5553 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,24 +8,28 @@ #include "rockchip-common.h" -#define CFG_IRAM_BASE 0xfff80000 +#define CFG_IRAM_BASE 0xfff80000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x03e00000\0" \ - "fdtoverlay_addr_r=0x03f00000\0" \ - "kernel_addr_r=0x00680000\0" \ - "ramdisk_addr_r=0x04000000\0" +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "kernel_comp_size=0x2000000\0" -#define CFG_EXTRA_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - ENV_MEM_LAYOUT_SETTINGS \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" -#endif +#endif /* __CONFIG_RK3308_COMMON_H */ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 2c40674..bd2bfe2 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -8,25 +8,28 @@ #include "rockchip-common.h" -#define CFG_IRAM_BASE 0xff090000 +#define CFG_IRAM_BASE 0xff090000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x01f00000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x06000000\0" \ - "kernel_comp_addr_r=0x08000000\0" \ +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ "kernel_comp_size=0x2000000\0" -#define CFG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" -#endif +#endif /* __CONFIG_RK3328_COMMON_H */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 4e75771..d652ae4 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,36 +8,36 @@ #include "rockchip-common.h" -#define CFG_IRAM_BASE 0xff8c0000 +#define CFG_IRAM_BASE 0xff8c0000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 #ifndef CONFIG_SPL_BUILD -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ - "script_offset_f=0xffe000\0" \ - "script_size_f=0x2000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x01f00000\0" \ - "fdtoverlay_addr_r=0x02000000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x06000000\0" \ - "kernel_comp_addr_r=0x08000000\0" \ - "kernel_comp_size=0x2000000\0" - #ifndef ROCKCHIP_DEVICE_SETTINGS #define ROCKCHIP_DEVICE_SETTINGS #endif -#define CFG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "kernel_comp_size=0x2000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" -#endif +#endif /* CONFIG_SPL_BUILD */ -#endif +#endif /* __CONFIG_RK3399_COMMON_H */ diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 48f9308..09b7b71 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ @@ -10,7 +10,7 @@ #include "rockchip-common.h" -#define CFG_IRAM_BASE 0xfdcc0000 +#define CFG_IRAM_BASE 0xfdcc0000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 @@ -28,10 +28,10 @@ "kernel_comp_size=0x8000000\0" #define CFG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" -#endif +#endif /* __CONFIG_RK3568_COMMON_H */ diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h index 7043061..e6654c2 100644 --- a/include/configs/rk3588_common.h +++ b/include/configs/rk3588_common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2021 Rockchip Electronics Co., Ltd * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. @@ -26,11 +26,11 @@ "ramdisk_addr_r=0x12180000\0" \ "kernel_comp_size=0x8000000\0" -#define CFG_EXTRA_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ENV_MEM_LAYOUT_SETTINGS \ - ROCKCHIP_DEVICE_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ "boot_targets=" BOOT_TARGETS "\0" #endif /* __CONFIG_RK3588_COMMON_H */ |