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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2024-04-11 17:29:45 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-05-01 22:40:00 +0800 |
| commit | fd55792e143f7ec46c5e70a8683183163d8c6878 (patch) | |
| tree | 445bc82a325414cb4597c6ab1f4f0c775aad3a1f | |
| parent | ff0de1f0557ed7d2dab47ba976a37347a1fdc432 (diff) | |
| download | u-boot-fd55792e143f7ec46c5e70a8683183163d8c6878.zip u-boot-fd55792e143f7ec46c5e70a8683183163d8c6878.tar.gz u-boot-fd55792e143f7ec46c5e70a8683183163d8c6878.tar.bz2 | |
riscv: andesv5: Set default cache line size to 64-bytes
The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/cpu/andesv5/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index f311291..e3efb0d 100644 --- a/arch/riscv/cpu/andesv5/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -1,6 +1,7 @@ config RISCV_NDS bool select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) |