diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2023-12-07 15:42:47 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2024-04-22 01:12:26 +0100 |
| commit | 25f07d2cc3c81763b2bf112a7edd24049554370d (patch) | |
| tree | 481e8a776b04242e580efe7a08cf1fc763b35313 | |
| parent | c209a7163a37196486d44c0529544953ac4e4db2 (diff) | |
| download | u-boot-25f07d2cc3c81763b2bf112a7edd24049554370d.zip u-boot-25f07d2cc3c81763b2bf112a7edd24049554370d.tar.gz u-boot-25f07d2cc3c81763b2bf112a7edd24049554370d.tar.bz2 | |
sunxi: sun8i_a83t: make more clock functions SPL only
In clock_sun8i_a83t.c, responsible for (mostly early) clock setup on the
Allwinner A83T SoC, many functions are only needed by the SPL, and are
thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun8i_a83t.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 198fe9d..9eeba08 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -46,7 +46,6 @@ void clock_init_safe(void) /* timestamp */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -70,7 +69,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -102,8 +100,9 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) { struct sunxi_ccm_reg * const ccm = |