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| author | Benjamin Hahn <B.Hahn@phytec.de> | 2024-03-06 17:18:32 +0100 |
|---|---|---|
| committer | Fabio Estevam <festevam@gmail.com> | 2024-03-11 08:42:44 -0300 |
| commit | 76832300a9c8b4a61cb7a49e0b9779e931abbc37 (patch) | |
| tree | 8f8dc6ee9e72a1e0d35d5e964b5d757387320675 | |
| parent | 110d321a56c3ea1824104ea6148efe040adf995d (diff) | |
| download | u-boot-76832300a9c8b4a61cb7a49e0b9779e931abbc37.zip u-boot-76832300a9c8b4a61cb7a49e0b9779e931abbc37.tar.gz u-boot-76832300a9c8b4a61cb7a49e0b9779e931abbc37.tar.bz2 | |
board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1
We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
| -rw-r--r-- | board/phytec/phycore_imx8mp/spl.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index d38f636..df15802 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -46,8 +46,10 @@ void spl_dram_init(void) if (!ret) phytec_print_som_info(NULL); - ret = phytec_get_rev(NULL); - if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) { + u8 rev = phytec_get_rev(NULL); + u8 somtype = phytec_get_som_type(NULL); + + if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) { dram_timing.ddrc_cfg[3].val = 0x1323; dram_timing.ddrc_cfg[4].val = 0x1e84800; dram_timing.ddrc_cfg[5].val = 0x7a0118; |