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| author | Tom Rini <trini@konsulko.com> | 2023-12-18 08:31:50 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-12-18 09:55:32 -0500 |
| commit | 1373ffde52e16af83fb14a1d228508a8caaa9996 (patch) | |
| tree | 03bb09d38a260233e3f5b9493d14c82dbd267299 | |
| parent | fdefb4e194c65777fa11479119adaa71651f41d4 (diff) | |
| parent | 97a897444235921ce19b4f8a3b27de6f5a9ab367 (diff) | |
| download | u-boot-1373ffde52e16af83fb14a1d228508a8caaa9996.zip u-boot-1373ffde52e16af83fb14a1d228508a8caaa9996.tar.gz u-boot-1373ffde52e16af83fb14a1d228508a8caaa9996.tar.bz2 | |
Merge tag 'v2024.01-rc5' into next
Prepare v2024.01-rc5
78 files changed, 1015 insertions, 2227 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index d77b9ff..25f2bb8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -117,7 +117,7 @@ F: drivers/mmc/snps_dw_mmc.c APPLE M1 SOC SUPPORT M: Mark Kettenis <kettenis@openbsd.org> S: Maintained -F: arch/arm/include/asm/arch-m1/ +F: arch/arm/include/asm/arch-apple/ F: arch/arm/mach-apple/ F: configs/apple_m1_defconfig F: drivers/iommu/apple_dart.c @@ -1528,7 +1528,6 @@ F: cmd/stackprot_test.c F: test/py/tests/test_stackprotector.py TARGET_BCMNS3 -M: Bharat Gooty <bharat.gooty@broadcom.com> M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> S: Maintained F: board/broadcom/bcmns3/ @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ef0e705..e9e58c5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -835,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ sun50i-h616-orangepi-zero2.dtb \ + sun50i-h618-orangepi-zero3.dtb \ sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ @@ -1516,6 +1517,8 @@ targets += $(dtb-y) # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 +DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format + PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index f2d6b18..c54a59e 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -93,6 +93,12 @@ &gpio4 { bootph-some-ram; + + usbh_en { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; }; &gpio5 { diff --git a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi index 3dd01e3..3b5f14e 100644 --- a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi +++ b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi @@ -7,6 +7,12 @@ usb0 = &usbotg1; display0 = &lcdif; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &usbotg1 { @@ -46,6 +52,10 @@ }; }; +&wdog1 { + bootph-pre-ram; +}; + &iomuxc { pinctrl_backlight: backlight { fsl,pins = < diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi index 49b992d..4f44598 100644 --- a/arch/arm/dts/imx7s-warp-u-boot.dtsi +++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi @@ -1,12 +1,12 @@ / { - aliases { - mmc0 = &usdhc3; - usb0 = &usbotg1; - }; + aliases { + mmc0 = &usdhc3; + usb0 = &usbotg1; + }; - chosen { - stdout-path = &uart1; - }; + chosen { + stdout-path = &uart1; + }; }; &aips3 { diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi index e0caf31..2bbc4a4 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi @@ -39,11 +39,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_pmic { @@ -83,5 +83,5 @@ }; &eeprom_som { - bootph-pre-ram; + bootph-all; }; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi index 15290e6..fc7315b 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi @@ -68,10 +68,7 @@ &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index d83852e..b5d7139 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -13,6 +13,9 @@ }; &emac0 { + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii"; phy-supply = <®_dcdce>; }; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts index 00fe28c..b3b1b86 100644 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts @@ -13,6 +13,8 @@ }; &emac0 { + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii-rxid"; phy-supply = <®_dldo1>; }; diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 47393ba..7a6151a 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -372,6 +372,22 @@ static struct mm_region t6020_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x400000000, + .phys = 0x400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x480000000, + .phys = 0x480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x580000000, .phys = 0x580000000, .size = SZ_512M, @@ -473,6 +489,22 @@ static struct mm_region t6022_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x400000000, + .phys = 0x400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x480000000, + .phys = 0x480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x580000000, .phys = 0x580000000, .size = SZ_512M, @@ -553,6 +585,22 @@ static struct mm_region t6022_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x2400000000, + .phys = 0x2400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2480000000, + .phys = 0x2480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x2580000000, .phys = 0x2580000000, .size = SZ_512M, diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 5cf97a5..4721995 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -56,6 +56,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), + PLL_1443X_RATE(900000000U, 300, 8, 0, 0), PLL_1443X_RATE(800000000U, 300, 9, 0, 0), PLL_1443X_RATE(750000000U, 250, 8, 0, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 6b4eb8d..9271de0 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -5,9 +5,6 @@ #include <config.h> -#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff) -#define U64_TO_U32_L(addr) ((addr) & 0xffffffff) - / { binman: binman { multiple-images; @@ -36,8 +33,7 @@ os = "U-Boot"; arch = "riscv"; compression = "none"; - load = <U64_TO_U32_H(CONFIG_TEXT_BASE) - U64_TO_U32_L(CONFIG_TEXT_BASE)>; + load = /bits/ 64 <CONFIG_TEXT_BASE>; uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; @@ -50,7 +46,7 @@ os = "Linux"; arch = "riscv"; compression = "none"; - load = <CONFIG_TEXT_BASE>; + load = /bits/ 64 <CONFIG_TEXT_BASE>; linux_blob: blob-ext { filename = "Image"; @@ -64,10 +60,8 @@ os = "opensbi"; arch = "riscv"; compression = "none"; - load = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR) - U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>; - entry = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR) - U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>; + load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; opensbi_blob: opensbi { filename = "fw_dynamic.bin"; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 13c47f7..6d2675d 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -533,6 +533,16 @@ #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + mmc0: mmc@16010000 { compatible = "starfive,jh7110-mmc"; reg = <0x0 0x16010000 0x0 0x10000>; diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 6a63661..c09e5c6 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -21,41 +21,36 @@ #include <linux/err.h> /* pending register */ -#define PENDING_REG(base) ((ulong)(base) + 0x1000) +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32)) /* enable register */ -#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32)) /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) /* priority register */ #define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) /* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */ -#define FIRST_AVAILABLE_BIT 0x2 -#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart)) #define PLICSW_PRIORITY_BASE 0x4 -#define PLICSW_INTERRUPT_PER_HART 0x1 DECLARE_GLOBAL_DATA_PTR; static int enable_ipi(int hart) { - unsigned int en; + u32 enable_bit = (hart + 1) % 32; - en = FIRST_AVAILABLE_BIT << hart; - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); + writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); return 0; } static void init_priority_ipi(int hart_num) { - uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw); + u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw); - for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) { - writel(1, &priority[i]); - } + for (int i = 0; i < hart_num; i++) + writel(1, &priority[i]); - return; + return; } int riscv_init_ipi(void) @@ -104,9 +99,10 @@ int riscv_init_ipi(void) int riscv_send_ipi(int hart) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw)); + writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); return 0; } @@ -123,10 +119,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw)); - *pending = !!(*pending & ipi); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); + *pending = !!(*pending & BIT(pending_bit)); return 0; } diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9131eda..4fe7266 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -631,9 +631,10 @@ clocks = <&clk_fixed>, <&clk_sandbox 1>, <&clk_sandbox 0>, + <&ccf 11>, <&clk_sandbox 3>, <&clk_sandbox 2>; - clock-names = "fixed", "i2c", "spi", "uart2", "uart1"; + clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1"; }; clk-test2 { @@ -654,6 +655,7 @@ ccf: clk-ccf { compatible = "sandbox,clk-ccf"; + #clock-cells = <1>; }; efi-media { diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h index 2b7dbca..d4e04ad 100644 --- a/arch/sandbox/include/asm/clk.h +++ b/arch/sandbox/include/asm/clk.h @@ -38,6 +38,7 @@ enum sandbox_clk_test_id { SANDBOX_CLK_TEST_ID_FIXED, SANDBOX_CLK_TEST_ID_SPI, SANDBOX_CLK_TEST_ID_I2C, + SANDBOX_CLK_TEST_ID_I2C_ROOT, SANDBOX_CLK_TEST_ID_DEVM1, SANDBOX_CLK_TEST_ID_DEVM2, SANDBOX_CLK_TEST_ID_DEVM_NULL, diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index bf9a114..a6761c2 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -30,6 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7 + u8 dmo_get_memcfg(void) { struct gpio_desc gpio[4]; @@ -58,8 +60,16 @@ u8 dmo_get_memcfg(void) int board_phys_sdram_size(phys_size_t *size) { u8 memcfg = dmo_get_memcfg(); + u8 ecc = 0; + + *size = 4ULL >> ((memcfg >> 1) & 0x3); + + if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) { + /* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */ + ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK; + } - *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G; + *size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0); return 0; } @@ -100,6 +110,12 @@ static void spl_dram_init(struct dram_timing_info *dram_timing_info[8]) } ddr_init(dram_timing_info[memcfg]); + + if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) { + printf("DDR: Inline ECC %sabled\n", + (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ? + "en" : "dis"); + } } void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad, diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c index 04cef3a..0ad4000 100644 --- a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c +++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c @@ -19,47 +19,66 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x1303 }, - { 0x3d400024, 0x1c79100 }, + { 0x3d400024, 0x1c7cf80 }, { 0x3d400064, 0x710106 }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400070, 0x7027fd4 }, +#else { 0x3d400070, 0x7027f90 }, +#endif { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc0030720 }, + { 0x3d4000d0, 0xc0030721 }, { 0x3d4000d4, 0xb80000 }, - { 0x3d4000dc, 0xe40036 }, - { 0x3d4000e0, 0x330000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0xf30000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x1e262028 }, - { 0x3d400104, 0x7073b }, + { 0x3d400100, 0x1f262028 }, + { 0x3d400104, 0x8083b }, { 0x3d40010c, 0xe0e000 }, { 0x3d400110, 0x11040a11 }, - { 0x3d400114, 0x2050e0e }, - { 0x3d400118, 0x1010008 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20700 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, { 0x3d400138, 0x10d }, { 0x3d400144, 0xbb005e }, - { 0x3d400180, 0x3a5001c }, - { 0x3d400184, 0x2f071e5 }, + { 0x3d400180, 0x3a6001d }, + { 0x3d400184, 0x2f071f4 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49b820c }, + { 0x3d400190, 0x4a3820e }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1b0c }, + { 0x3d4001b4, 0x230e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x810191a }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9141c1c }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400200, 0x14 }, +#else { 0x3d400200, 0x17 }, +#endif + { 0x3d400208, 0x0 }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d40020c, 0x14141400 }, +#else { 0x3d40020c, 0x0 }, +#endif { 0x3d400210, 0x1f1f }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x4040404 }, +#else { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, +#endif { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, @@ -78,7 +97,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -88,7 +107,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x1d }, @@ -97,13 +116,13 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, + { 0x3d4020f4, 0x599 }, { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -113,7 +132,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0x8 }, @@ -122,7 +141,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -260,16 +279,16 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x212149, 0xeba }, { 0x213049, 0xeba }, { 0x213149, 0xeba }, - { 0x43, 0xe7 }, - { 0x1043, 0xe7 }, - { 0x2043, 0xe7 }, - { 0x3043, 0xe7 }, - { 0x4043, 0xe7 }, - { 0x5043, 0xe7 }, - { 0x6043, 0xe7 }, - { 0x7043, 0xe7 }, - { 0x8043, 0xe7 }, - { 0x9043, 0xe7 }, + { 0x43, 0x3ff }, + { 0x1043, 0x3ff }, + { 0x2043, 0x3ff }, + { 0x3043, 0x3ff }, + { 0x4043, 0x3ff }, + { 0x5043, 0x3ff }, + { 0x6043, 0x3ff }, + { 0x7043, 0x3ff }, + { 0x8043, 0x3ff }, + { 0x9043, 0x3ff }, { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, @@ -319,19 +338,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, }; @@ -1061,7 +1076,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xe94 }, + { 0x54003, 0xe96 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1070,26 +1085,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0x3336 }, + { 0x54032, 0xf400 }, + { 0x54033, 0xf33f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0x3336 }, + { 0x54038, 0xf400 }, + { 0x54039, 0xf33f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1111,25 +1126,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1151,25 +1166,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1180,7 +1195,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xe94 }, + { 0x54003, 0xe96 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1190,26 +1205,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0x3336 }, + { 0x54032, 0xf400 }, + { 0x54033, 0xf33f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0x3336 }, + { 0x54038, 0xf400 }, + { 0x54039, 0xf33f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1699,9 +1714,9 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x419 }, + { 0x2000b, 0x41a }, { 0x2000c, 0xe9 }, - { 0x2000d, 0x91c }, + { 0x2000d, 0x91d }, { 0x2000e, 0x2c }, { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, @@ -1804,8 +1819,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 3733mts 1D */ - .drate = 3733, + /* P0 3600mts 1D */ + .drate = 3600, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1840,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 3733mts 2D */ - .drate = 3733, + /* P0 3600mts 2D */ + .drate = 3600, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1860,19 @@ struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32 = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, 400, 100, }, + .fsp_table = { 3600, 400, 100, }, }; + +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} +#endif diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index cfc4b65..a3600c8 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -68,6 +68,11 @@ int data_modul_imx_edm_sbc_board_power_init(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); + /* DRAM Vdd1 always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d); + /* DRAM Vdd2/Vddq always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d); + /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 2709c9c..cdd0d0d 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -54,8 +54,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SCSI_AHCI imply AHCI_PCI imply E1000 - imply NVME imply PCI + imply NVME_PCI imply PCIE_ECAM_GENERIC imply DM_RNG imply SCSI diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c b/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c deleted file mode 100644 index 8803fbf..0000000 --- a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c +++ /dev/null @@ -1,1849 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Generated code from MX8M_DDR_tool v3.20 using RPAv20 - * - 1x Micron MT53E128M32D2DS-046 32bit dual-channel for total of 512MiB - * - imx8mm-gw7903 - * - * Align with uboot version: - * imx_v2019.04_5.4.x and above version - * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: - * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h> - */ - -#include <linux/kernel.h> -#include <asm/arch/ddr.h> - -static struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x203 }, - { 0x3d400024, 0x3a980 }, - { 0x3d400064, 0x5b0062 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, - { 0x3d4000ec, 0x16004d }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x401 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0x68 }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x70e1617 }, - { 0x3d400200, 0x1f }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0xf0f0707 }, - { 0x3d40021c, 0xf0f }, - { 0x3d400250, 0x29001701 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1 }, - { 0x3d402024, 0x7d00 }, - { 0x3d402050, 0x20d040 }, - { 0x3d402064, 0xc000d }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, - { 0x3d4020ec, 0x16004d }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0xe }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1 }, - { 0x3d403024, 0x1f40 }, - { 0x3d403050, 0x20d040 }, - { 0x3d403064, 0x30004 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x4 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x4 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x2 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x1 }, - { 0x130a2, 0x2 }, - { 0x130a3, 0x3 }, - { 0x130a4, 0x4 }, - { 0x130a5, 0x5 }, - { 0x130a6, 0x6 }, - { 0x130a7, 0x7 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x120024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x220024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x20056, 0x3 }, - { 0x120056, 0x3 }, - { 0x220056, 0x3 }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0xdc }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0xdc }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0xdc }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, - { 0x200c7, 0x21 }, - { 0x1200c7, 0x21 }, - { 0x2200c7, 0x21 }, - { 0x200ca, 0x24 }, - { 0x1200ca, 0x24 }, - { 0x2200ca, 0x24 }, -}; - -/* ddr phy trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -/* P0 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xf }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x630 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x630 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x630 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x630 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x630 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x630 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x630 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x630 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x630 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x630 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x630 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x630 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x630 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xa }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x2 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x900a4, 0x10 }, - { 0x900a5, 0x10 }, - { 0x900a6, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x623 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x623 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a7, 0x0 }, - { 0x900a8, 0x790 }, - { 0x900a9, 0x11a }, - { 0x900aa, 0x8 }, - { 0x900ab, 0x7aa }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x10 }, - { 0x900ae, 0x7b2 }, - { 0x900af, 0x2a }, - { 0x900b0, 0x0 }, - { 0x900b1, 0x7c8 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x0 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xc }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x0 }, - { 0x90169, 0x8 }, - { 0x9016a, 0x8 }, - { 0x9016b, 0x448 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0xf }, - { 0x9016e, 0x7c0 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x0 }, - { 0x90171, 0xe8 }, - { 0x90172, 0x109 }, - { 0x90173, 0x47 }, - { 0x90174, 0x630 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x618 }, - { 0x90178, 0x109 }, - { 0x90179, 0x8 }, - { 0x9017a, 0xe0 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x7c8 }, - { 0x9017e, 0x109 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x8140 }, - { 0x90181, 0x10c }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x2a }, - { 0x90026, 0x6a }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x2000b, 0x5d }, - { 0x2000c, 0xbb }, - { 0x2000d, 0x753 }, - { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x60 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x120010, 0x5a }, - { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x2003a, 0x2 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3000mts 1D */ - .drate = 3000, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_512mb = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, -}; diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 7bfd1b5..56c6e2b 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1211,9 +1211,9 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x34b }, - { 0x2000c, 0xbb }, - { 0x2000d, 0x753 }, + { 0x2000b, 0x465 }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, { 0x2000e, 0x2c }, { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, @@ -1323,42 +1323,42 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x1203 }, - { 0x3d400024, 0x16e3600 }, - { 0x3d400064, 0x5b0087 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a00b4 }, { 0x3d400070, 0x7027f90 }, { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x402 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0x8d }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0xbc }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, + { 0x3d400190, 0x49f820e }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, + { 0x3d4001b4, 0x1f0e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0x699 }, - { 0x3d400108, 0x70e1617 }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x1f }, { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, @@ -1379,7 +1379,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc0012 }, @@ -1404,7 +1404,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0x599 }, - { 0x3d403020, 0x1001 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30005 }, @@ -1436,36 +1436,36 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x100a0, 0x0 }, { 0x100a1, 0x1 }, - { 0x100a2, 0x3 }, - { 0x100a3, 0x2 }, - { 0x100a4, 0x5 }, - { 0x100a5, 0x4 }, - { 0x100a6, 0x7 }, - { 0x100a7, 0x6 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x2 }, - { 0x120a3, 0x3 }, - { 0x120a4, 0x4 }, - { 0x120a5, 0x5 }, - { 0x120a6, 0x6 }, - { 0x120a7, 0x7 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x3 }, - { 0x130a3, 0x4 }, - { 0x130a4, 0x5 }, - { 0x130a5, 0x2 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -1500,7 +1500,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, + { 0x200c5, 0x18 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -1509,11 +1509,11 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1a3 }, + { 0x20024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1a3 }, + { 0x120024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1a3 }, + { 0x220024, 0x1e3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -1579,7 +1579,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, + { 0x20008, 0x3e8 }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -1644,7 +1644,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1653,26 +1653,26 @@ struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1763,7 +1763,7 @@ struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1773,26 +1773,26 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1802,8 +1802,8 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { { - /* P0 3000mts 1D */ - .drate = 3000, + /* P0 4000mts 1D */ + .drate = 4000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg_1gb_single_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die), @@ -1823,8 +1823,8 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die), }, { - /* P0 3000mts 2D */ - .drate = 3000, + /* P0 4000mts 2D */ + .drate = 4000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die), @@ -1843,7 +1843,7 @@ struct dram_timing_info dram_timing_1gb_single_die = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 4000, 400, 100, }, }; /* @@ -1856,43 +1856,44 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, - { 0x3d400020, 0x1203 }, - { 0x3d400024, 0x16e3600 }, - { 0x3d400064, 0x5b00d2 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, { 0x3d400070, 0x7027f90 }, { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x401 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0xd8 }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, + { 0x3d400190, 0x49f820e}, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, + { 0x3d4001b4, 0x1f0e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x70e1617 }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x17 }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, @@ -1911,7 +1912,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, @@ -1926,7 +1927,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x1d }, @@ -1935,8 +1936,8 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1001 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, @@ -1951,7 +1952,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0x8 }, @@ -1960,7 +1961,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -1968,36 +1969,36 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x100a0, 0x0 }, { 0x100a1, 0x1 }, - { 0x100a2, 0x3 }, - { 0x100a3, 0x2 }, - { 0x100a4, 0x5 }, - { 0x100a5, 0x4 }, - { 0x100a6, 0x7 }, - { 0x100a7, 0x6 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x2 }, - { 0x120a3, 0x3 }, - { 0x120a4, 0x4 }, - { 0x120a5, 0x5 }, - { 0x120a6, 0x6 }, - { 0x120a7, 0x7 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x3 }, - { 0x130a3, 0x4 }, - { 0x130a4, 0x5 }, - { 0x130a5, 0x2 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -2032,7 +2033,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, + { 0x200c5, 0x18 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -2041,11 +2042,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1a3 }, + { 0x20024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1a3 }, + { 0x120024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1a3 }, + { 0x220024, 0x1e3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -2111,7 +2112,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, + { 0x20008, 0x3e8 }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -2175,7 +2176,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -2184,26 +2185,26 @@ static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x310 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -2294,7 +2295,7 @@ static struct dram_cfg_param ddr_fsp2_cfg_4gb_dual_die[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -2304,26 +2305,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -2333,8 +2334,8 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { { - /* P0 3000mts 1D */ - .drate = 3000, + /* P0 4000mts 1D */ + .drate = 4000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg_4gb_dual_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4gb_dual_die), @@ -2354,8 +2355,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4gb_dual_die), }, { - /* P0 3000mts 2D */ - .drate = 3000, + /* P0 4000mts 2D */ + .drate = 4000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg_4gb_dual_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4gb_dual_die), @@ -2374,5 +2375,5 @@ struct dram_timing_info dram_timing_4gb_dual_die = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 4000, 400, 100, }, }; diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index a39ae58..0902a1d 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -238,12 +238,12 @@ int ft_board_setup(void *fdt, struct bd_info *bd) if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); - if (pcbrev > 'B') { + if (pcbrev > 'B' && pcbrev < 'E') { printf("adjusting dt for %s\n", base_model); /* - * revC replaced PCIe 5-port switch with 4-port - * which changed ethernet1 PCIe GbE + * revC/D/E has PCIe 4-port switch which changes + * ethernet1 PCIe GbE: * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0 * to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0 */ diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS index 303db14..220ee21 100644 --- a/board/pine64/rockpro64_rk3399/MAINTAINERS +++ b/board/pine64/rockpro64_rk3399/MAINTAINERS @@ -1,5 +1,4 @@ ROCKPRO64 -M: Akash Gajjar <akash@openedev.com> M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: board/pine64/rockpro64_rk3399 diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index c7e412b..acdb840 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -93,7 +93,6 @@ F: configs/rock-4se-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi ROCK-PI-4 -M: Akash Gajjar <akash@openedev.com> M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/rock-pi-4-rk3399_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 0061437..f556857 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -455,6 +455,11 @@ M: Jernej Skrabec <jernej.skrabec@siol.net> S: Maintained F: configs/orangepi_zero2_defconfig +ORANGEPI ZERO 3 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/orangepi_zero3_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara <andre.przywara@arm.com> S: Maintained diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index e23f9af..7a59a78 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -66,7 +66,7 @@ int dram_init(void) } static iomux_v3_cfg_t const flash_detection_pads[] = { - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL) | MUX_MODE_SION, }; static iomux_v3_cfg_t const uart1_pads[] = { @@ -193,9 +193,9 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* - * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST + * Enable GPIO SION on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST * is pulled high with 4.7k for eMMC devices. This allows to reliably - * detect eMMC/NAND flash + * detect eMMC vs NAND flash. */ imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads)); gpio_request(FLASH_DET_GPIO, "flash-detection-gpio"); diff --git a/board/tq/tqma6/tqma6q.cfg b/board/tq/tqma6/tqma6q.cfg index a49489a..a345c4d 100644 --- a/board/tq/tqma6/tqma6q.cfg +++ b/board/tq/tqma6/tqma6q.cfg @@ -36,7 +36,7 @@ DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00003030 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index d46bff5..00060f7 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -160,7 +160,6 @@ static int efiload_read_file(struct bootflow *bflow, ulong addr) if (ret) return log_msg_ret("read", ret); bflow->buf = map_sysmem(addr, bflow->size); - bflow->flags |= BOOTFLOWF_STATIC_BUF; set_efi_bootdev(desc, bflow); @@ -313,6 +312,7 @@ static int distro_efi_try_bootflow_files(struct udevice *dev, */ } else { log_debug("No device tree available\n"); + bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT; } return 0; @@ -323,7 +323,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) char file_addr[17], fname[256]; char *tftp_argv[] = {"tftp", file_addr, fname, NULL}; struct cmd_tbl cmdtp = {}; /* dummy */ - const char *addr_str, *fdt_addr_str; + const char *addr_str, *fdt_addr_str, *bootfile_name; int ret, arch, size; ulong addr, fdt_addr; char str[36]; @@ -339,7 +339,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) ret = env_set("bootp_vci", str); if (ret) return log_msg_ret("vcs", ret); - ret = env_set_ulong("bootp_arch", arch); + ret = env_set_hex("bootp_arch", arch); if (ret) return log_msg_ret("ars", ret); @@ -360,6 +360,12 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) return log_msg_ret("sz", -EINVAL); bflow->size = size; + /* bootfile should be setup by dhcp*/ + bootfile_name = env_get("bootfile"); + if (!bootfile_name) + return log_msg_ret("bootfile_name", ret); + bflow->fname = strdup(bootfile_name); + /* do the hideous EFI hack */ efi_set_bootdev("Net", "", bflow->fname, map_sysmem(addr, 0), bflow->size); @@ -385,6 +391,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) bflow->fdt_addr = fdt_addr; } else { log_debug("No device tree available\n"); + bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT; } bflow->state = BOOTFLOWST_READY; @@ -396,6 +403,12 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow) { int ret; + /* + * bootmeth_efi doesn't allocate any buffer neither for blk nor net device + * set flag to avoid freeing static buffer. + */ + bflow->flags |= BOOTFLOWF_STATIC_BUF; + if (bootmeth_uses_network(bflow)) { /* we only support reading from one device, so ignore 'dev' */ ret = distro_efi_read_bootflow_net(bflow); @@ -422,13 +435,11 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) return log_msg_ret("read", ret); /* - * use the provided device tree if available, else fall back to - * the control FDT + * use the provided device tree if not using the built-in fdt */ - if (bflow->fdt_fname) + if (bflow->flags & ~BOOTFLOWF_USE_BUILTIN_FDT) fdt = bflow->fdt_addr; - else - fdt = (ulong)map_to_sysmem(gd->fdt_blob); + } else { /* * This doesn't actually work for network devices: @@ -441,8 +452,17 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) fdt = env_get_hex("fdt_addr_r", 0); } - if (efi_binary_run(map_sysmem(kernel, 0), 0, map_sysmem(fdt, 0))) - return log_msg_ret("run", -EINVAL); + if (bflow->flags & BOOTFLOWF_USE_BUILTIN_FDT) { + log_debug("Booting with built-in fdt\n"); + if (efi_binary_run(map_sysmem(kernel, 0), 0, + EFI_FDT_USE_INTERNAL)) + return log_msg_ret("run", -EINVAL); + } else { + log_debug("Booting with external fdt\n"); + if (efi_binary_run(map_sysmem(kernel, 0), 0, + map_sysmem(fdt, 0))) + return log_msg_ret("run", -EINVAL); + } return 0; } diff --git a/cmd/efi_common.c b/cmd/efi_common.c index f405609..1aa2351 100644 --- a/cmd/efi_common.c +++ b/cmd/efi_common.c @@ -17,10 +17,8 @@ void efi_show_tables(struct efi_system_table *systab) for (i = 0; i < systab->nr_tables; i++) { struct efi_configuration_table *tab = &systab->tables[i]; - char guid_str[37]; - uuid_bin_to_str(tab->guid.b, guid_str, 1); - printf("%p %pUl %s\n", tab->table, guid_str, + printf("%p %pUl %s\n", tab->table, tab->guid.b, uuid_guid_get_str(tab->guid.b) ?: "(unknown)"); } } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index fc284a5..cf7ffc9 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -378,7 +378,7 @@ config SPL_STACK default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x118000 if MACH_SUN50I_H6 - default 0x58000 if MACH_SUN50I_H616 + default 0x52a00 if MACH_SUN50I_H616 default 0x40000 if MACH_SUN8I_R528 default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x18000 if MACH_SUN9I diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 056c1fb..d11a31e 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -65,6 +65,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y CONFIG_CPU=y +CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 2a3958b..755bccb 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -56,6 +56,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index 405ce3a..af8dace 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -61,6 +61,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 20a38a3..6a4244e 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -162,6 +162,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index 7ee4540..f5914ac 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -169,6 +169,8 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 54c02df..3f9b0e3 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -165,6 +165,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 6799f0c..50c21d5 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -167,6 +167,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 0b59971..683053b 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -71,6 +71,7 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index ba74b24..b1c267a 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MESON_SPIFC=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index bc0bf9b..49d628b 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -63,6 +63,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index f13735e..98aed84 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_USB1_VBUS_PIN="PC16" CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -19,6 +20,7 @@ CONFIG_SYS_I2C_SPEED=400000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y +CONFIG_AXP305_POWER=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig new file mode 100644 index 0000000..5a019fe --- /dev/null +++ b/configs/orangepi_zero3_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e +CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee +CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 +CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624 +CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_CLK=792 +CONFIG_USB1_VBUS_PIN="PC16" +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP313_POWER=y +CONFIG_SPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 1eee1e6..3af968d 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -70,6 +70,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 48364c7..5b615da 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -76,6 +76,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -95,3 +97,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig index e941576..b795681 100644 --- a/configs/radxa-zero2_defconfig +++ b/configs/radxa-zero2_defconfig @@ -52,6 +52,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index b15e7d2..7b39a63 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y @@ -133,3 +134,7 @@ CONFIG_USB_EHCI_PCI=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_PCI=y CONFIG_USB_KEYBOARD=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_STARFIVE=y diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index 318951e..e805e09 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 +CONFIG_AXP305_POWER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index 23902de..5f8db12 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -424,15 +424,59 @@ space. See existing code for examples. VPL (Verifying Program Loader) ------------------------------ -Sandbox provides an example build of vpl called `sandbox_vpl`. This can be run -using:: +Sandbox provides an example build of vpl called `sandbox_vpl`. To build it: - /path/to/sandbox_vpl/tpl/u-boot-tpl -D +.. code-block:: bash + + make sandbox_vpl_defconfig all + +This can be run using: + +.. code-block:: bash + + ./tpl/u-boot-tpl -d u-boot.dtb It starts up TPL (first-stage init), then VPL, then runs SPL and finally U-Boot proper, following the normal flow for a verified boot. At present, no verification is actually implemented. +Here is an example trace:: + + U-Boot TPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + U-Boot VPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from vbe_simple + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + U-Boot SPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from vbe_simple + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + + U-Boot 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + + Reset Status: COLD + Model: sandbox + DRAM: 256 MiB + using memory 0x1b576000-0x1f578000 for malloc() + + Warning: host_lo MAC addresses don't match: + Address in ROM is 96:cd:ef:82:78:51 + Address in environment is 02:00:11:22:33:44 + Core: 103 devices, 51 uclasses, devicetree: board + MMC: + Loading Environment from nowhere... OK + In: serial,cros-ec-keyb,usbkbd + Out: serial,vidconsole + Err: serial,vidconsole + Model: sandbox + Net: eth0: host_lo, eth1: host_enp14s0, eth2: host_eth6, eth3: host_wlp15s0, eth4: host_virbr0, eth5: host_docker0, eth6: eth@10002000 + Hit any key to stop autoboot: 1 + Debugging the init sequence --------------------------- diff --git a/doc/board/allwinner/sunxi.rst b/doc/board/allwinner/sunxi.rst index 797222d..d0c89b9 100644 --- a/doc/board/allwinner/sunxi.rst +++ b/doc/board/allwinner/sunxi.rst @@ -251,8 +251,7 @@ the SPI flash content from Linux, using the `MTD utils`_:: # apt-get install mtd-utils # mtdinfo - # mtd_debug erase /dev/mtdX 0 0xf0000 - # mtd_debug write /dev/mtdX 0 0xf0000 u-boot-sunxi-with-spl.bin + # flashcp -v u-boot-sunxi-with-spl.bin /dev/mtdX ``/dev/mtdX`` needs to be replaced with the respective device name, as listed in the output of ``mtdinfo``. diff --git a/doc/build/clang.rst b/doc/build/clang.rst index cc26550..09bb988 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -11,14 +11,6 @@ The ARM backend can be instructed not to use the r9 and x18 registers using supported inline assembly is needed to get and set the r9 or x18 value. This leads to larger code then strictly necessary, but at least works. -**NOTE:** target compilation only work for _some_ ARM boards at the moment. -Also AArch64 is not supported currently due to a lack of private libgcc -support. Boards which reassign gd in c will also fail to compile, but there is -in no strict reason to do so in the ARM world, since crt0.S takes care of this. -These assignments can be avoided by changing the init calls but this is not in -mainline yet. - - Debian based ------------ @@ -28,14 +20,20 @@ Required packages can be installed via apt, e.g. sudo apt-get install clang -Note that we still use binutils for some tools so we must continue to set -CROSS_COMPILE. To compile U-Boot with Clang on Linux without IAS use e.g. +We make use of the CROSS_COMPILE variable to derive the build target which is +passed as the --target parameter to clang. + +The CROSS_COMPILE variable further determines the paths to other build +tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as' +instead of the LLVM integrated assembler (IAS). + +Here is an example demonstrating building U-Boot for the Raspberry Pi 2 +using clang: .. code-block:: bash make HOSTCC=clang rpi_2_defconfig - make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- \ - CC="clang -target arm-linux-gnueabi" -j8 + make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8 It can also be used to compile sandbox: diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 37e9fc1..8fe77f2 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -72,7 +72,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2024.01-rc4 was released on Mon 04 December 2023. -.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023. +* U-Boot v2024.01-rc5 was released on Mon 18 December 2023. .. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index ba73d0d..5a6962f 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -363,7 +363,7 @@ A Custodian has additional privileges and can: * Awaiting Upstream - * Superseeded + * Superseded * Deferred @@ -399,7 +399,7 @@ today. Not all states are used by all custodians. and has not merged yet to master, or has queued the patch up to be submitted to be merged, but has not yet. -* Superseeded: Patches are marked as 'superseeded' when the poster submits a +* Superseded: Patches are marked as 'superseded' when the poster submits a new version of these patches. * Deferred: Deferred usually means the patch depends on something else that diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 6eb2b81..d2e5a1a 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -66,7 +66,7 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate) const struct clk_ops *rate_ops = composite->rate_ops; struct clk *clk_rate = composite->rate; - if (rate && rate_ops) + if (rate && rate_ops && rate_ops->set_rate) return rate_ops->set_rate(clk_rate, rate); else return clk_get_rate(clk); diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3b5e3f9..3e9d68f 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -640,6 +640,7 @@ int clk_enable(struct clk *clk) if (CONFIG_IS_ENABLED(CLK_CCF)) { /* Take id 0 as a non-valid clk, such as dummy */ if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + ops = clk_dev_ops(clkp->dev); if (clkp->enable_count) { clkp->enable_count++; return 0; @@ -699,6 +700,7 @@ int clk_disable(struct clk *clk) if (CONFIG_IS_ENABLED(CLK_CCF)) { if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + ops = clk_dev_ops(clkp->dev); if (clkp->flags & CLK_IS_CRITICAL) return 0; diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index a5a3461..6ede1b4 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -18,17 +18,19 @@ int clk_register(struct clk *clk, const char *drv_name, const char *name, const char *parent_name) { - struct udevice *parent; + struct udevice *parent = NULL; struct driver *drv; int ret; - ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); - if (ret) { - log_err("%s: failed to get %s device (parent of %s)\n", - __func__, parent_name, name); - } else { - log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, - parent->name, parent); + if (parent_name) { + ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); + if (ret) { + log_err("%s: failed to get %s device (parent of %s)\n", + __func__, parent_name, name); + } else { + log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, + parent->name, parent); + } } drv = lists_driver_lookup_name(drv_name); diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index fedcdd4..38184e2 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -284,6 +284,7 @@ static int sandbox_clk_ccf_probe(struct udevice *dev) U_BOOT_DRIVER(sandbox_clk_ccf) = { .name = "sandbox_clk_ccf", .id = UCLASS_CLK, + .ops = &ccf_clk_ops, .probe = sandbox_clk_ccf_probe, .of_match = sandbox_clk_ccf_test_ids, }; diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index 5807a45..c695b69 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -15,6 +15,7 @@ static const char * const sandbox_clk_test_names[] = { [SANDBOX_CLK_TEST_ID_FIXED] = "fixed", [SANDBOX_CLK_TEST_ID_SPI] = "spi", [SANDBOX_CLK_TEST_ID_I2C] = "i2c", + [SANDBOX_CLK_TEST_ID_I2C_ROOT] = "i2c_root", }; int sandbox_clk_test_get(struct udevice *dev) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a835541..a386948 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "i2c5_apb", "apb0", OFFSET(JH7110_SYSCLK_I2C5_APB))); + /* Watchdog clocks */ + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB), + starfive_clk_gate(priv->reg, + "wdt_apb", "apb0", + OFFSET(JH7110_SYSCLK_WDT_APB))); + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE), + starfive_clk_gate(priv->reg, + "wdt_core", "oscillator", + OFFSET(JH7110_SYSCLK_WDT_CORE))); /* enable noc_bus_stg_axi clock */ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk)) diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index fd8b411..45e1a70 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -111,11 +111,16 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(1000)); dram_disable_bypass(); break; + case 3734: case 3733: case 3732: dram_pll_init(MHZ(933)); dram_disable_bypass(); break; + case 3600: + dram_pll_init(MHZ(900)); + dram_disable_bypass(); + break; case 3200: dram_pll_init(MHZ(800)); dram_disable_bypass(); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 97057de..ed7eced 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -615,7 +615,7 @@ config FS_LOADER ie. the FPGA device. config SPL_FS_LOADER - bool "Enable loader driver for file system" + bool "Enable loader driver for file system in SPL" depends on SPL help This is file system generic loader which can be used to load diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 732b076..abed392 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -224,6 +224,11 @@ config SPI_FLASH_XTX Add support for various XTX (XTX Technology Limited) SPI flash chips (XT25xxx). +config SPI_FLASH_ZBIT + bool "ZBIT SPI flash support" + help + Add support for Zbit Semiconductor Inc. SPI flash chips (ZB25xxx). + endif config SPI_FLASH_USE_4K_SECTORS diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3cb132d..f86e7ff 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -572,5 +572,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif +#ifdef CONFIG_SPI_FLASH_ZBIT + /* Zbit Semiconductor Inc. */ + { INFO("zb25vq128", 0x5e4018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, +#endif { }, }; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 2395720..33b8bc1 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -56,7 +56,6 @@ choice depends on ARCH_SUNXI default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 - default AXP305_POWER if MACH_SUN50I_H616 default AXP818_POWER if MACH_SUN8I_A83T default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 07fc494..5697261 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -344,6 +344,13 @@ config WDT_STM32MP Enable the STM32 watchdog (IWDG) driver. Enable support to configure STM32's on-SoC watchdog. +config WDT_STARFIVE + bool "StarFive watchdog timer support" + depends on WDT + imply WATCHDOG + help + Enable support for the watchdog timer of StarFive JH7110 SoC. + config WDT_SUNXI bool "Allwinner sunxi watchdog timer support" depends on WDT && ARCH_SUNXI diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index eef786f..5520d3d 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o +obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c new file mode 100644 index 0000000..ee9ec4c --- /dev/null +++ b/drivers/watchdog/starfive_wdt.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Starfive Watchdog driver + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include <clk.h> +#include <dm.h> +#include <reset.h> +#include <wdt.h> +#include <linux/iopoll.h> + +/* JH7110 Watchdog register define */ +#define STARFIVE_WDT_JH7110_LOAD 0x000 +#define STARFIVE_WDT_JH7110_VALUE 0x004 +#define STARFIVE_WDT_JH7110_CONTROL 0x008 /* + * [0]: reset enable; + * [1]: interrupt enable && watchdog enable + * [31:2]: reserved. + */ +#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */ +#define STARFIVE_WDT_JH7110_IMS 0x014 +#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */ + +/* WDOGCONTROL */ +#define STARFIVE_WDT_ENABLE 0x1 +#define STARFIVE_WDT_EN_SHIFT 0 +#define STARFIVE_WDT_RESET_EN 0x1 +#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1 + +/* WDOGLOCK */ +#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551 + +/* WDOGINTCLR */ +#define STARFIVE_WDT_INTCLR 0x1 +#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */ + +#define STARFIVE_WDT_MAXCNT 0xffffffff +#define STARFIVE_WDT_DEFAULT_TIME (15) +#define STARFIVE_WDT_DELAY_US 0 +#define STARFIVE_WDT_TIMEOUT_US 10000 + +/* module parameter */ +#define STARFIVE_WDT_EARLY_ENA 0 + +struct starfive_wdt_variant { + unsigned int control; /* Watchdog Control Resgister for reset enable */ + unsigned int load; /* Watchdog Load register */ + unsigned int reload; /* Watchdog Reload Control register */ + unsigned int enable; /* Watchdog Enable Register */ + unsigned int value; /* Watchdog Counter Value Register */ + unsigned int int_clr; /* Watchdog Interrupt Clear Register */ + unsigned int unlock; /* Watchdog Lock Register */ + unsigned int int_status; /* Watchdog Interrupt Status Register */ + + u32 unlock_key; + char enrst_shift; + char en_shift; + bool intclr_check; /* whether need to check it before clearing interrupt */ + char intclr_ava_shift; + bool double_timeout; /* The watchdog need twice timeout to reboot */ +}; + +struct starfive_wdt_priv { + void __iomem *base; + struct clk *core_clk; + struct clk *apb_clk; + struct reset_ctl_bulk *rst; + const struct starfive_wdt_variant *variant; + unsigned long freq; + u32 count; /* count of timeout */ + u32 reload; /* restore the count */ +}; + +/* Register layout and configuration for the JH7110 */ +static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = { + .control = STARFIVE_WDT_JH7110_CONTROL, + .load = STARFIVE_WDT_JH7110_LOAD, + .enable = STARFIVE_WDT_JH7110_CONTROL, + .value = STARFIVE_WDT_JH7110_VALUE, + .int_clr = STARFIVE_WDT_JH7110_INTCLR, + .unlock = STARFIVE_WDT_JH7110_LOCK, + .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY, + .int_status = STARFIVE_WDT_JH7110_IMS, + .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT, + .en_shift = STARFIVE_WDT_EN_SHIFT, + .intclr_check = false, + .double_timeout = true, +}; + +static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt) +{ + int ret; + + ret = clk_enable(wdt->apb_clk); + if (ret) + return ret; + + ret = clk_enable(wdt->core_clk); + if (ret) { + clk_disable(wdt->apb_clk); + return ret; + } + + return 0; +} + +static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt) +{ + clk_disable(wdt->core_clk); + clk_disable(wdt->apb_clk); +} + +/* Write unlock-key to unlock. Write other value to lock. */ +static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt) +{ + writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +static void starfive_wdt_lock(struct starfive_wdt_priv *wdt) +{ + writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +/* enable watchdog interrupt to reset/reboot */ +static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->control); + val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift; + writel(val, wdt->base + wdt->variant->control); +} + +/* waiting interrupt can be free to clear */ +static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt) +{ + u32 value; + + return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value, + !(value & BIT(wdt->variant->intclr_ava_shift)), + STARFIVE_WDT_TIMEOUT_US); +} + +/* clear interrupt signal before initialization or reload */ +static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt) +{ + int ret; + + if (wdt->variant->intclr_check) { + ret = starfive_wdt_wait_int_free(wdt); + if (ret) + return ret; + } + writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr); + + return 0; +} + +static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt, + u32 val) +{ + writel(val, wdt->base + wdt->variant->load); +} + +/* enable watchdog */ +static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift; + writel(val, wdt->base + wdt->variant->enable); +} + +/* disable watchdog */ +static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift); + writel(val, wdt->base + wdt->variant->enable); +} + +static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt, + u32 count) +{ + starfive_wdt_set_count(wdt, count); + + /* 7100 need set any value to reload register and could reload value to counter */ + if (wdt->variant->reload) + writel(0x1, wdt->base + wdt->variant->reload); +} + +static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + /* disable watchdog, to be safe */ + starfive_wdt_disable(wdt); + + starfive_wdt_enable_reset(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + wdt->count = (timeout_ms / 1000) * wdt->freq; + if (wdt->variant->double_timeout) + wdt->count /= 2; + + starfive_wdt_set_count(wdt, wdt->count); + starfive_wdt_enable(wdt); + +exit: + starfive_wdt_lock(wdt); + return ret; +} + +static int starfive_wdt_stop(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + starfive_wdt_disable(wdt); + starfive_wdt_lock(wdt); + + return 0; +} + +static int starfive_wdt_reset(struct udevice *dev) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + starfive_wdt_set_reload_count(wdt, wdt->count); + +exit: + starfive_wdt_lock(wdt); + + return ret; +} + +static const struct wdt_ops starfive_wdt_ops = { + .start = starfive_wdt_start, + .stop = starfive_wdt_stop, + .reset = starfive_wdt_reset, +}; + +static int starfive_wdt_probe(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + int ret; + + ret = starfive_wdt_enable_clock(wdt); + if (ret) + return ret; + + ret = reset_deassert_bulk(wdt->rst); + if (ret) + goto err_reset; + + wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev); + + wdt->freq = clk_get_rate(wdt->core_clk); + if (!wdt->freq) { + ret = -EINVAL; + goto err_get_freq; + } + + return 0; + +err_get_freq: + reset_assert_bulk(wdt->rst); +err_reset: + starfive_wdt_disable_clock(wdt); + + return ret; +} + +static int starfive_wdt_of_to_plat(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + wdt->base = (void *)dev_read_addr(dev); + if (!wdt->base) + return -ENODEV; + + wdt->apb_clk = devm_clk_get(dev, "apb"); + if (IS_ERR(wdt->apb_clk)) + return -ENODEV; + + wdt->core_clk = devm_clk_get(dev, "core"); + if (IS_ERR(wdt->core_clk)) + return -ENODEV; + + wdt->rst = devm_reset_bulk_get(dev); + if (IS_ERR(wdt->rst)) + return -ENODEV; + + return 0; +} + +static const struct udevice_id starfive_wdt_ids[] = { + { + .compatible = "starfive,jh7110-wdt", + .data = (ulong)&starfive_wdt_jh7110_variant + }, { + /* sentinel */ + } +}; + +U_BOOT_DRIVER(starfive_wdt) = { + .name = "starfive_wdt", + .id = UCLASS_WDT, + .of_match = starfive_wdt_ids, + .priv_auto = sizeof(struct starfive_wdt_priv), + .probe = starfive_wdt_probe, + .of_to_plat = starfive_wdt_of_to_plat, + .ops = &starfive_wdt_ops, +}; diff --git a/include/bootflow.h b/include/bootflow.h index fede8f2..4211287 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -45,10 +45,12 @@ enum bootflow_state_t { * CONFIG_OF_HAS_PRIOR_STAGE is enabled * @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather * than being allocated by malloc(). + * @BOOTFLOWF_USE_BUILTIN_FDT : Indicates that current bootflow uses built-in FDT */ enum bootflow_flags_t { BOOTFLOWF_USE_PRIOR_FDT = 1 << 0, BOOTFLOWF_STATIC_BUF = 1 << 1, + BOOTFLOWF_USE_BUILTIN_FDT = 1 << 2, }; /** diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 03f8ed1..7a9f4af 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -101,7 +101,6 @@ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define MODULE_EXTRA_ENV_SETTINGS \ - "variant=-emmc\0" \ EMMC_ANDROID_BOOTCMD #endif diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index ff43113..29c7447 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -40,6 +40,7 @@ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ "fdt_addr_r=0x46000000\0" \ + "fdtoverlay_addr_r=0x45800000\0" \ "scriptaddr=0x43900000\0" \ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \ diff --git a/lib/Kconfig b/lib/Kconfig index 9ae846e..37ac14f 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1002,7 +1002,7 @@ config GENERATE_SMBIOS_TABLE Check http://www.dmtf.org/standards/smbios for details. - See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in + See also SYSINFO_SMBIOS which allows SMBIOS values to be provided in the devicetree. endmenu diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c index 2209410..c5eb816 100644 --- a/lib/efi/efi_app.c +++ b/lib/efi/efi_app.c @@ -12,18 +12,21 @@ #include <cpu_func.h> #include <debug_uart.h> #include <dm.h> +#include <efi.h> +#include <efi_api.h> #include <errno.h> #include <init.h> #include <malloc.h> +#include <sysreset.h> +#include <uuid.h> #include <asm/global_data.h> #include <linux/err.h> #include <linux/types.h> -#include <efi.h> -#include <efi_api.h> -#include <sysreset.h> +#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/root.h> +#include <mapmem.h> DECLARE_GLOBAL_DATA_PTR; @@ -320,6 +323,19 @@ int dm_scan_other(bool pre_reloc_only) return 0; } +static void scan_tables(struct efi_system_table *sys_table) +{ + efi_guid_t acpi = EFI_ACPI_TABLE_GUID; + uint i; + + for (i = 0; i < sys_table->nr_tables; i++) { + struct efi_configuration_table *tab = &sys_table->tables[i]; + + if (!memcmp(&tab->guid, &acpi, sizeof(efi_guid_t))) + gd_set_acpi_start(map_to_sysmem(tab->table)); + } +} + /** * efi_main() - Start an EFI image * @@ -354,6 +370,8 @@ efi_status_t EFIAPI efi_main(efi_handle_t image, return ret; } + scan_tables(priv->sys_table); + /* * We could store the EFI memory map here, but it changes all the time, * so this is only useful for debugging. diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 0a2cb6e..24d33d5 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -51,9 +51,7 @@ obj-y += efi_console.o obj-y += efi_device_path.o obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o -ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) obj-y += efi_dt_fixup.o -endif obj-y += efi_file.o obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o obj-y += efi_image_loader.o diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 56d97f2..e815fa0 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -1262,8 +1262,6 @@ efi_status_t efi_env_set_load_options(efi_handle_t handle, return ret; } -#if !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) - /** * copy_fdt() - Copy the device tree to a new location available to EFI * @@ -1337,8 +1335,6 @@ static void *get_config_table(const efi_guid_t *guid) return NULL; } -#endif /* !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) */ - /** * efi_install_fdt() - install device tree * @@ -1358,18 +1354,15 @@ static void *get_config_table(const efi_guid_t *guid) */ efi_status_t efi_install_fdt(void *fdt) { + struct bootm_headers img = { 0 }; + efi_status_t ret; + /* * The EBBR spec requires that we have either an FDT or an ACPI table * but not both. */ -#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) - if (fdt) { + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt) log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n"); - return EFI_SUCCESS; - } -#else - struct bootm_headers img = { 0 }; - efi_status_t ret; if (fdt == EFI_FDT_USE_INTERNAL) { const char *fdt_opt; @@ -1402,6 +1395,12 @@ efi_status_t efi_install_fdt(void *fdt) return EFI_LOAD_ERROR; } + /* Create memory reservations as indicated by the device tree */ + efi_carve_out_dt_rsv(fdt); + + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) + return EFI_SUCCESS; + /* Prepare device tree for payload */ ret = copy_fdt(&fdt); if (ret) { @@ -1414,9 +1413,6 @@ efi_status_t efi_install_fdt(void *fdt) return EFI_LOAD_ERROR; } - /* Create memory reservations as indicated by the device tree */ - efi_carve_out_dt_rsv(fdt); - efi_try_purge_kaslr_seed(fdt); if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) { @@ -1433,7 +1429,6 @@ efi_status_t efi_install_fdt(void *fdt) log_err("ERROR: failed to install device tree\n"); return ret; } -#endif /* GENERATE_ACPI_TABLE */ return EFI_SUCCESS; } diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 3767fa2..644bebe 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -1342,7 +1342,7 @@ static efi_status_t efi_disconnect_all_drivers const efi_guid_t *protocol, efi_handle_t child_handle) { - efi_uintn_t number_of_drivers, tmp; + efi_uintn_t number_of_drivers; efi_handle_t *driver_handle_buffer; efi_status_t r, ret; @@ -1353,27 +1353,13 @@ static efi_status_t efi_disconnect_all_drivers if (!number_of_drivers) return EFI_SUCCESS; - tmp = number_of_drivers; while (number_of_drivers) { - ret = EFI_CALL(efi_disconnect_controller( + r = EFI_CALL(efi_disconnect_controller( handle, driver_handle_buffer[--number_of_drivers], child_handle)); - if (ret != EFI_SUCCESS) - goto reconnect; - } - - free(driver_handle_buffer); - return ret; - -reconnect: - /* Reconnect all disconnected drivers */ - for (; number_of_drivers < tmp; number_of_drivers++) { - r = EFI_CALL(efi_connect_controller(handle, - &driver_handle_buffer[number_of_drivers], - NULL, true)); if (r != EFI_SUCCESS) - EFI_PRINT("Failed to reconnect controller\n"); + ret = r; } free(driver_handle_buffer); @@ -1412,6 +1398,13 @@ static efi_status_t efi_uninstall_protocol r = efi_disconnect_all_drivers(handle, protocol, NULL); if (r != EFI_SUCCESS) { r = EFI_ACCESS_DENIED; + /* + * This will reconnect all controllers of the handle, even ones + * that were not connected before. This can be done better + * but we are following the EDKII implementation on this for + * now + */ + EFI_CALL(efi_connect_controller(handle, NULL, NULL, true)); goto out; } /* Close protocol */ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8dc6ec8..16bbc27 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -339,7 +339,12 @@ cmd_capsule_esl_gen = \ $(shell sed "s:ESL_BIN_FILE:$(capsule_esl_path):" $(capsule_esl_input_file) > $@) $(obj)/.capsule_esl.dtsi: FORCE +ifeq ($(CONFIG_EFI_CAPSULE_ESL_FILE),"") + $(error "CONFIG_EFI_CAPSULE_ESL_FILE is empty, EFI capsule authentication \ + public key must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled") +else $(call cmd_capsule_esl_gen) +endif capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in capsule_esl_dtsi = .capsule_esl.dtsi diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index e4ebb93..61dad8d 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -19,16 +19,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) { struct clk *clk, *pclk; - struct udevice *dev; + struct udevice *dev, *test_dev; long long rate; int ret; #if CONFIG_IS_ENABLED(CLK_CCF) + struct clk clk_ccf; const char *clkname; int clkid, i; #endif /* Get the device using the clk device */ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &test_dev)); /* Test for clk_get_by_id() */ ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk); @@ -63,6 +65,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_parent_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); @@ -87,6 +92,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ut_asserteq_str("pll3_80m", pclk->dev->name); ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags); + rate = clk_set_rate(clk, 80000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 80000000); @@ -108,13 +116,23 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, 60000000); + #if CONFIG_IS_ENABLED(CLK_CCF) /* Test clk tree enable/disable */ + + ret = clk_get_by_index(test_dev, SANDBOX_CLK_TEST_ID_I2C_ROOT, &clk_ccf); + ut_assertok(ret); + ut_asserteq_str("clk-ccf", clk_ccf.dev->name); + ut_asserteq(clk_ccf.id, SANDBOX_CLK_I2C_ROOT); + ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk); ut_assertok(ret); ut_asserteq_str("i2c_root", clk->dev->name); + ut_asserteq(clk->id, SANDBOX_CLK_I2C_ROOT); - ret = clk_enable(clk); + ret = clk_enable(&clk_ccf); ut_assertok(ret); ret = sandbox_clk_enable_count(clk); |