diff options
| author | Fabio Estevam <festevam@gmail.com> | 2024-03-08 17:13:15 -0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-22 11:10:39 -0400 |
| commit | bcbd1364cb0f32c3879a9c58ab8d61532e0bc4cd (patch) | |
| tree | 9230df5812139cd8706910f6174205558f2c46ad | |
| parent | 5397daaed8994000f2b3480896df9c163dea4375 (diff) | |
| download | u-boot-bcbd1364cb0f32c3879a9c58ab8d61532e0bc4cd.zip u-boot-bcbd1364cb0f32c3879a9c58ab8d61532e0bc4cd.tar.gz u-boot-bcbd1364cb0f32c3879a9c58ab8d61532e0bc4cd.tar.bz2 | |
clk: clk-imx8qxp: Add LPUART IPG entries
Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
the colibri-imx8qxp board no longer boots.
The reason is that the imx8qxp clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X
Acked-by: Sean Anderson <seanga2@gmail.com>
| -rw-r--r-- | drivers/clk/imx/clk-imx8qxp.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 8bf7e32..d900d4c 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -88,20 +88,23 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; - case IMX8QXP_UART0_IPG_CLK: case IMX8QXP_UART0_CLK: + case IMX8QXP_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART1_CLK: + case IMX8QXP_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART2_CLK: + case IMX8QXP_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART3_CLK: + case IMX8QXP_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -170,18 +173,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART0_CLK: + case IMX8QXP_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART1_CLK: + case IMX8QXP_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART2_CLK: + case IMX8QXP_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART3_CLK: + case IMX8QXP_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -263,18 +270,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable) pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART0_CLK: + case IMX8QXP_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART1_CLK: + case IMX8QXP_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART2_CLK: + case IMX8QXP_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART3_CLK: + case IMX8QXP_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; |