diff options
| author | Simon Glass <sjg@chromium.org> | 2023-09-19 21:00:05 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng@tinylab.org> | 2023-09-22 06:03:46 +0800 |
| commit | 8ebca32b2d48d5e21e5c49c0dc03b10051b68ba6 (patch) | |
| tree | 9395e2b3396a6ae3cba183eaac0e5ab12a79b61c | |
| parent | 2c6b979ec163afe72211eca571daee352a030c85 (diff) | |
| download | u-boot-8ebca32b2d48d5e21e5c49c0dc03b10051b68ba6.zip u-boot-8ebca32b2d48d5e21e5c49c0dc03b10051b68ba6.tar.gz u-boot-8ebca32b2d48d5e21e5c49c0dc03b10051b68ba6.tar.bz2 | |
x86: Set the CPU vendor in SPL
We don't read this information in 64-bit mode, since we don't have the
macros for doing it. Set it to Intel by default. This allows the TSC timer
to work correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/x86/cpu/x86_64/cpu.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index d1c3873..2647bff 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -8,8 +8,11 @@ #include <cpu_func.h> #include <debug_uart.h> #include <init.h> +#include <asm/cpu.h> #include <asm/global_data.h> +DECLARE_GLOBAL_DATA_PTR; + int cpu_has_64bit(void) { return true; @@ -38,6 +41,10 @@ int x86_mp_init(void) int x86_cpu_reinit_f(void) { + /* set the vendor to Intel so that native_calibrate_tsc() works */ + gd->arch.x86_vendor = X86_VENDOR_INTEL; + gd->arch.has_mtrr = true; + return 0; } |