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| author | Frank Wunderlich <frank-w@public-files.de> | 2020-08-13 10:20:46 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-08-19 17:38:15 -0400 |
| commit | fee276ee315ceff64900777b0b46cdafd88d1cfe (patch) | |
| tree | 9d076ec381018521a5db19f0a0e9a3e122ce14bb | |
| parent | ffbcde248d5197d998a9398057bc22b11628e9e4 (diff) | |
| download | u-boot-fee276ee315ceff64900777b0b46cdafd88d1cfe.zip u-boot-fee276ee315ceff64900777b0b46cdafd88d1cfe.tar.gz u-boot-fee276ee315ceff64900777b0b46cdafd88d1cfe.tar.bz2 | |
reset: add basic reset controller for pciesys
bind reset controller to pciesys
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7622.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index bd86b5b..d53ed69 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs); } +static int mt7622_pciesys_bind(struct udevice *dev) +{ + int ret = 0; + + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { +// PCIESYS uses in linux also 0x34 = ETHSYS reset controller + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + static int mt7622_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); @@ -710,6 +724,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = { .id = UCLASS_CLK, .of_match = mt7622_pciesys_compat, .probe = mt7622_pciesys_probe, + .bind = mt7622_pciesys_bind, .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; |