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| author | Peng Fan <peng.fan@nxp.com> | 2023-04-28 12:08:29 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-05-21 16:54:40 +0200 |
| commit | 59ecc85bcc4acf96db30e51688d5708e75a3c4f6 (patch) | |
| tree | 0392b1f3bc981dd678ca4379083f87556c961162 | |
| parent | 0079893920d8db47a6a1ac94790050867e38ec74 (diff) | |
| download | u-boot-59ecc85bcc4acf96db30e51688d5708e75a3c4f6.zip u-boot-59ecc85bcc4acf96db30e51688d5708e75a3c4f6.tar.gz u-boot-59ecc85bcc4acf96db30e51688d5708e75a3c4f6.tar.bz2 | |
imx9: clock: clear HW_CTRL_SEL
The HW_CTRL_SEL should be cleared when configuring PLL to avoid
potential glitch
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/mach-imx/imx9/clock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index a5f95fb..38e4cbb 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -206,6 +206,9 @@ int configure_intpll(enum ccm_clk_src pll, u32 freq) return -EPERM; } + /* Clear PLL HW CTRL SEL */ + setbits_le32(®->ctrl.reg_clr, PLL_CTRL_HW_CTRL_SEL); + /* Bypass the PLL to ref */ writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set); |