diff options
author | Mark Kettenis <kettenis@openbsd.org> | 2023-05-02 21:30:40 +0200 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-05-30 15:13:44 -0400 |
commit | 4a97874d3576bd60f4c674cb528b98d960a06b4a (patch) | |
tree | 9c3c0354fef110328572d7a86ad7df3328eedba9 | |
parent | bd6a247593742596a83d6e36bebb45cb78a4017e (diff) | |
download | u-boot-4a97874d3576bd60f4c674cb528b98d960a06b4a.zip u-boot-4a97874d3576bd60f4c674cb528b98d960a06b4a.tar.gz u-boot-4a97874d3576bd60f4c674cb528b98d960a06b4a.tar.bz2 |
arm: apple: Add initial Apple M2 Pro/Max support
Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but
need a tweaked memory map. USB, NVMe, UART and WDT are working
with the existing drivers.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
-rw-r--r-- | arch/arm/mach-apple/board.c | 109 |
1 files changed, 106 insertions, 3 deletions
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 1604642..d501948 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -343,6 +343,107 @@ static struct mm_region t6002_mem_map[] = { } }; +/* Apple M2 Pro/Max */ + +static struct mm_region t6020_mem_map[] = { + { + /* I/O */ + .virt = 0x280000000, + .phys = 0x280000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x340000000, + .phys = 0x340000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x380000000, + .phys = 0x380000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xf00000000, + .phys = 0xf00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x1300000000, + .phys = 0x1300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 16UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map; int board_init(void) @@ -379,12 +480,14 @@ void build_mem_map(void) if (of_machine_is_compatible("apple,t8103") || of_machine_is_compatible("apple,t8112")) mem_map = t8103_mem_map; - else if (of_machine_is_compatible("apple,t6000")) - mem_map = t6000_mem_map; - else if (of_machine_is_compatible("apple,t6001")) + else if (of_machine_is_compatible("apple,t6000") || + of_machine_is_compatible("apple,t6001")) mem_map = t6000_mem_map; else if (of_machine_is_compatible("apple,t6002")) mem_map = t6002_mem_map; + else if (of_machine_is_compatible("apple,t6020") || + of_machine_is_compatible("apple,t6021")) + mem_map = t6020_mem_map; else panic("Unsupported SoC\n"); |