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authorPratyush Yadav <p.yadav@ti.com>2021-06-26 00:47:20 +0530
committerJagan Teki <jagan@amarulasolutions.com>2021-06-28 12:02:39 +0530
commitb862765c7c9a64640ce557bc10a10b4f20e8584b (patch)
treef4123efd62c01cbad1f3bf11ecdb380a4968ac76
parent4d40e82663fe5ed8b65242bc28b3faaf838f5dcc (diff)
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mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode
The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in Octal DTR mode. Use that information to send the correct Read SR command. Some controllers might have trouble reading just 1 byte in DTR mode. So, when we are in DTR mode read 2 bytes and discard the second. This shows no side effects with the two flashes I tested: Micron mt35xu512aba and Cypress s28hs512t. Update Read FSR to mimic Read SR because they share the same characteristics. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
-rw-r--r--drivers/mtd/spi/spi-nor-core.c60
1 files changed, 54 insertions, 6 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b3b04db..b9d3101 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -380,16 +380,40 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
*/
static int read_sr(struct spi_nor *nor)
{
+ struct spi_mem_op op;
int ret;
- u8 val;
+ u8 val[2];
+ u8 addr_nbytes, dummy;
+
+ if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+ addr_nbytes = nor->rdsr_addr_nbytes;
+ dummy = nor->rdsr_dummy;
+ } else {
+ addr_nbytes = 0;
+ dummy = 0;
+ }
+
+ op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0),
+ SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
+ SPI_MEM_OP_DUMMY(dummy, 0),
+ SPI_MEM_OP_DATA_IN(1, NULL, 0));
+
+ spi_nor_setup_op(nor, &op, nor->reg_proto);
+
+ /*
+ * We don't want to read only one byte in DTR mode. So, read 2 and then
+ * discard the second byte.
+ */
+ if (spi_nor_protocol_is_dtr(nor->reg_proto))
+ op.data.nbytes = 2;
- ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
+ ret = spi_nor_read_write_reg(nor, &op, val);
if (ret < 0) {
pr_debug("error %d reading SR\n", (int)ret);
return ret;
}
- return val;
+ return *val;
}
/*
@@ -399,16 +423,40 @@ static int read_sr(struct spi_nor *nor)
*/
static int read_fsr(struct spi_nor *nor)
{
+ struct spi_mem_op op;
int ret;
- u8 val;
+ u8 val[2];
+ u8 addr_nbytes, dummy;
+
+ if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+ addr_nbytes = nor->rdsr_addr_nbytes;
+ dummy = nor->rdsr_dummy;
+ } else {
+ addr_nbytes = 0;
+ dummy = 0;
+ }
+
+ op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
+ SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
+ SPI_MEM_OP_DUMMY(dummy, 0),
+ SPI_MEM_OP_DATA_IN(1, NULL, 0));
+
+ spi_nor_setup_op(nor, &op, nor->reg_proto);
+
+ /*
+ * We don't want to read only one byte in DTR mode. So, read 2 and then
+ * discard the second byte.
+ */
+ if (spi_nor_protocol_is_dtr(nor->reg_proto))
+ op.data.nbytes = 2;
- ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
+ ret = spi_nor_read_write_reg(nor, &op, val);
if (ret < 0) {
pr_debug("error %d reading FSR\n", ret);
return ret;
}
- return val;
+ return *val;
}
/*