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| author | Simon Glass <sjg@chromium.org> | 2023-03-14 17:59:51 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng@tinylab.org> | 2023-03-27 09:38:44 +0800 |
| commit | f1d87db49bdc1cc97e0ee5636b20f1a99c4fcaf2 (patch) | |
| tree | 100356b9ca46d9a3ac2369c3e2d71ea26b3a1966 | |
| parent | 8be7b4629e87ff8db08dd087c81d58129d029bad (diff) | |
| download | u-boot-f1d87db49bdc1cc97e0ee5636b20f1a99c4fcaf2.zip u-boot-f1d87db49bdc1cc97e0ee5636b20f1a99c4fcaf2.tar.gz u-boot-f1d87db49bdc1cc97e0ee5636b20f1a99c4fcaf2.tar.bz2 | |
x86: minnowmax: Fix up adjustment of CONFIG_TEXT_BASE
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Add documentation on how to make this change safely.
Fixes: 66e2c665f3b6 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 2 | ||||
| -rw-r--r-- | configs/minnowmax_defconfig | 1 | ||||
| -rw-r--r-- | doc/board/intel/minnowmax.rst | 15 |
3 files changed, 15 insertions, 3 deletions
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 68e0510..466309f 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -206,7 +206,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 679b6e3..b93c0d7 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -18,6 +18,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst index 1ba25b5..d0286bd 100644 --- a/doc/board/intel/minnowmax.rst +++ b/doc/board/intel/minnowmax.rst @@ -54,9 +54,9 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 <spare> +5f0000 MRC cache CONFIG_ENABLE_MRC_CACHE +600000 u-boot-dtb.bin CONFIG_TEXT_BASE 6ef000 Environment CONFIG_ENV_OFFSET -6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE -700000 u-boot-dtb.bin CONFIG_TEXT_BASE 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 <spare> (depends on size of fsp.bin) @@ -68,3 +68,14 @@ Overall ROM image size is controlled by CONFIG_ROM_SIZE. Note that the debug version of the FSP is bigger in size. If this version is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of the default value 0xfffc0000. + +If you want to change CONFIG_TEXT_BASE from the current value of ffe00000 +you need to check a few other things. CONFIG_SYS_MONITOR_BASE should +automatically update to be the same as CONFIG_TEXT_BASE but +CONFIG_SYS_MONITOR_LEN may need to be adjusted too. It must cover the space +from the start of U-Boot to the end of the RAM, since the 16-bit boot needs to +be able to jump to U-Boot. See the end of arch/x86/lib/fsp1/fsp_car.S which +has these values. + +Also check the MRC cache address in the devicetree ("rw-mrc-cache"). It must +not overlap with U-Boot. |