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| author | Xiaowei Bao <xiaowei.bao@nxp.com> | 2020-07-09 23:31:35 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-07-27 14:24:15 +0530 |
| commit | 57fcc13738f1a28a39a916f6358569875d3d0820 (patch) | |
| tree | bfbff60a7bd843b1e2336d1c131afd511e6fda59 | |
| parent | fd00c53fb399708a210e365d768b35e8692a46b8 (diff) | |
| download | u-boot-57fcc13738f1a28a39a916f6358569875d3d0820.zip u-boot-57fcc13738f1a28a39a916f6358569875d3d0820.tar.gz u-boot-57fcc13738f1a28a39a916f6358569875d3d0820.tar.bz2 | |
armv8: dts: ls1046a: Add the PCIe EP node
Add the PCIe EP node for ls1046a.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| -rw-r--r-- | arch/arm/dts/fsl-ls1046a.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 8673a5d..3f11d6c 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -257,6 +257,17 @@ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie_ep@3400000 { + compatible = "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x80000 + 0x00 0x034c0000 0x0 0x40000 + 0x40 0x00000000 0x8 0x00000000>; + reg-names = "regs", "ctrl", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + big-endian; + }; + pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ @@ -274,6 +285,17 @@ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie_ep@3500000 { + compatible = "fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x80000 + 0x00 0x035c0000 0x0 0x40000 + 0x48 0x00000000 0x8 0x00000000>; + reg-names = "regs", "ctrl", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + big-endian; + }; + pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ @@ -290,6 +312,17 @@ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie_ep@3600000 { + compatible = "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x80000 + 0x00 0x036c0000 0x0 0x40000 + 0x50 0x00000000 0x8 0x00000000>; + reg-names = "regs", "ctrl", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + big-endian; + }; + sata: sata@3200000 { compatible = "fsl,ls1046a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ |