ARM: rmobile: Update H2 Lager

The H2 Lager port was broken since some time. This patch updates
the H2 Lager port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

7 files changed, 526 insertions, 203 deletions

diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dts b/arch/arm/dts/r8a7790-lager-u-boot.dts
index a3f1577..a42d61c 100644
--- a/arch/arm/dts/r8a7790-lager-u-boot.dts
+++ b/arch/arm/dts/r8a7790-lager-u-boot.dts
@@ -8,3 +8,7 @@
 
 #include "r8a7790-lager.dts"
 #include "r8a7790-u-boot.dtsi"
+
+&scif0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index a8835f6..d8c6a8b 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -55,6 +55,9 @@ config TARGET_LAGER
 	bool "Lager board"
 	select DM
 	select DM_SERIAL
+	select SUPPORT_SPL
+	select USE_TINY_PRINTF
+	select SPL_TINY_MEMSET
 
 config TARGET_KZM9G
 	bool "KZM9D board"
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
index 0e44c69..379368f 100644
--- a/board/renesas/lager/Makefile
+++ b/board/renesas/lager/Makefile
@@ -6,4 +6,8 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= lager.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y	:= lager_spl.o
+else
+obj-y	:= lager.o qos.o
+endif
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 3566bcc..505efb5 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -57,105 +57,60 @@ void s_init(void)
 	qos_init();
 }
 
-#define TMU0_MSTP125	(1 << 25)
-#define SCIF0_MSTP721	(1 << 21)
-#define ETHER_MSTP813	(1 << 13)
-#define MMC1_MSTP305    (1 << 5)
+#define TMU0_MSTP125	BIT(25)
 
-#define MSTPSR3		0xE6150048
-#define SMSTPCR3	0xE615013C
-#define SDHI0_MSTP314	(1 << 14)
-#define SDHI1_MSTP313	(1 << 13)
-#define SDHI2_MSTP312	(1 << 12)
-
-#define SD2CKCR		0xE6150078
-#define SD2_97500KHZ	0x7
+#define SD1CKCR		0xE6150078
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
 
 int board_early_init_f(void)
 {
-	/* TMU0 */
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-	/* SCIF0 */
-	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-	/* ETHER */
-	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-	/* eMMC */
-	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
-	/* SDHI0, 2 */
-	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
 
 	/*
 	 * SD0 clock is set to 97.5MHz by default.
-	 * Set SD2 to the 97.5MHz as well.
+	 * Set SD1 and SD2 to the 97.5MHz as well.
 	 */
-	writel(SD2_97500KHZ, SD2CKCR);
+	writel(SD_97500KHZ, SD1CKCR);
+	writel(SD_97500KHZ, SD2CKCR);
 
 	return 0;
 }
 
-DECLARE_GLOBAL_DATA_PTR;
+#define ETHERNET_PHY_RESET	185	/* GPIO 5 31 */
+
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	/* Init PFC controller */
-	r8a7790_pinmux_init();
-
-	/* ETHER Enable */
-	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
-	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
-	gpio_request(GPIO_FN_ETH_RXD0, NULL);
-	gpio_request(GPIO_FN_ETH_RXD1, NULL);
-	gpio_request(GPIO_FN_ETH_LINK, NULL);
-	gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
-	gpio_request(GPIO_FN_ETH_MDIO, NULL);
-	gpio_request(GPIO_FN_ETH_TXD1, NULL);
-	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
-	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
-	gpio_request(GPIO_FN_ETH_TXD0, NULL);
-	gpio_request(GPIO_FN_ETH_MDC, NULL);
-	gpio_request(GPIO_FN_IRQ0, NULL);
-
-	gpio_request(GPIO_GP_5_31, NULL);	/* PHY_RST */
-	gpio_direction_output(GPIO_GP_5_31, 0);
-	mdelay(20);
-	gpio_set_value(GPIO_GP_5_31, 1);
-	udelay(1);
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
+	mdelay(10);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
 
 	return 0;
 }
 
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
 {
-	int ret = -ENODEV;
-
-#ifdef CONFIG_SH_ETHER
-	u32 val;
-	unsigned char enetaddr[6];
+	if (fdtdec_setup_memory_size() != 0)
+		return -EINVAL;
 
-	ret = sh_eth_initialize(bis);
-	if (!eth_env_get_enetaddr("ethaddr", enetaddr))
-		return ret;
-
-	/* Set Mac address */
-	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
-	    enetaddr[2] << 8 | enetaddr[3];
-	writel(val, CXR24);
-
-	val = enetaddr[4] << 8 | enetaddr[5];
-	writel(val, CXR25);
+	return 0;
+}
 
-#endif
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
 
-	return ret;
+	return 0;
 }
 
-/* lager has KSZ8041NL/RNL */
-#define PHY_CONTROL1	0x1E
-#define PHY_LED_MODE	0xC0000
+/* KSZ8041NL/RNL */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC0000
 #define PHY_LED_MODE_ACK	0x4000
 int board_phy_config(struct phy_device *phydev)
 {
@@ -167,97 +122,44 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-int board_mmc_init(bd_t *bis)
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
 {
-	int ret = -ENODEV;
-
-#ifdef CONFIG_SH_MMCIF
-	gpio_request(GPIO_FN_MMC1_D0, NULL);
-	gpio_request(GPIO_FN_MMC1_D1, NULL);
-	gpio_request(GPIO_FN_MMC1_D2, NULL);
-	gpio_request(GPIO_FN_MMC1_D3, NULL);
-	gpio_request(GPIO_FN_MMC1_D4, NULL);
-	gpio_request(GPIO_FN_MMC1_D5, NULL);
-	gpio_request(GPIO_FN_MMC1_D6, NULL);
-	gpio_request(GPIO_FN_MMC1_D7, NULL);
-	gpio_request(GPIO_FN_MMC1_CLK, NULL);
-	gpio_request(GPIO_FN_MMC1_CMD, NULL);
-
-	ret = mmcif_mmc_init();
-#endif
-
-#ifdef CONFIG_SH_SDHI
-	gpio_request(GPIO_FN_SD0_DAT0, NULL);
-	gpio_request(GPIO_FN_SD0_DAT1, NULL);
-	gpio_request(GPIO_FN_SD0_DAT2, NULL);
-	gpio_request(GPIO_FN_SD0_DAT3, NULL);
-	gpio_request(GPIO_FN_SD0_CLK, NULL);
-	gpio_request(GPIO_FN_SD0_CMD, NULL);
-	gpio_request(GPIO_FN_SD0_CD, NULL);
-	gpio_request(GPIO_FN_SD2_DAT0, NULL);
-	gpio_request(GPIO_FN_SD2_DAT1, NULL);
-	gpio_request(GPIO_FN_SD2_DAT2, NULL);
-	gpio_request(GPIO_FN_SD2_DAT3, NULL);
-	gpio_request(GPIO_FN_SD2_CLK, NULL);
-	gpio_request(GPIO_FN_SD2_CMD, NULL);
-	gpio_request(GPIO_FN_SD2_CD, NULL);
+	struct udevice *dev;
+	const u8 pmic_bus = 2;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
 
-	/*
-	 * SDHI 0
-	 * need JP3 set to pin-1 side on board.
-	 */
-	gpio_request(GPIO_GP_5_24, NULL);
-	gpio_request(GPIO_GP_5_29, NULL);
-	gpio_direction_output(GPIO_GP_5_24, 1);	/* power on */
-	gpio_direction_output(GPIO_GP_5_29, 1);	/* 1: 3.3V, 0: 1.8V */
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
 
-	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
-			   SH_SDHI_QUIRK_16BIT_BUF);
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
 	if (ret)
-		return ret;
+		hang();
 
-	/* SDHI 2 */
-	gpio_request(GPIO_GP_5_25, NULL);
-	gpio_request(GPIO_GP_5_30, NULL);
-	gpio_direction_output(GPIO_GP_5_25, 1);	/* power on */
-	gpio_direction_output(GPIO_GP_5_30, 1);	/* 1: 3.3V, 0: 1.8V */
+	data |= BIT(1);
 
-	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
-	return ret;
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
 }
 
-
-int dram_init(void)
+enum env_location env_get_location(enum env_operation op, int prio)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	const u32 load_magic = 0xb33fc0de;
 
-	return 0;
-}
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
 
-const struct rmobile_sysinfo sysinfo = {
-	CONFIG_ARCH_RMOBILE_BOARD_STRING
-};
-
-void reset_cpu(ulong addr)
-{
-	u8 val;
+	if (prio)
+		return ENVL_UNKNOWN;
 
-	i2c_set_bus_num(3); /* PowerIC connected to ch3 */
-	i2c_init(400000, 0);
-	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
-	val |= 0x02;
-	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	return ENVL_SPI_FLASH;
 }
-
-static const struct sh_serial_platdata serial_platdata = {
-	.base = SCIF0_BASE,
-	.type = PORT_SCIF,
-	.clk = 14745600,
-	.clk_mode = EXT_CLK,
-};
-
-U_BOOT_DEVICE(lager_serials) = {
-	.name = "serial_sh",
-	.platdata = &serial_platdata,
-};
diff --git a/board/renesas/lager/lager_spl.c b/board/renesas/lager/lager_spl.c
new file mode 100644
index 0000000..5730eb2
--- /dev/null
+++ b/board/renesas/lager/lager_spl.c
@@ -0,0 +1,396 @@
+/*
+ * board/renesas/lager/lager_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125	BIT(25)
+#define SCIF0_MSTP721	BIT(21)
+#define QSPI_MSTP917	BIT(17)
+
+#define SD2CKCR		0xE615026C
+#define SD_97500KHZ	0x7
+
+struct reg_config {
+	u16	off;
+	u32	val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+	while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+		;
+}
+
+static void spl_init_sys(void)
+{
+	u32 r0 = 0;
+
+	writel(0xa5a5a500, 0xe6020004);
+	writel(0xa5a5a500, 0xe6030004);
+
+	asm volatile(
+		/* ICIALLU - Invalidate I$ to PoU */
+		"mcr	15, 0, %0, cr7, cr5, 0	\n"
+		/* BPIALL - Invalidate branch predictors */
+		"mcr	15, 0, %0, cr7, cr5, 6	\n"
+		/* Set SCTLR[IZ] */
+		"mrc	15, 0, %0, cr1, cr0, 0	\n"
+		"orr	%0, #0x1800		\n"
+		"mcr	15, 0, %0, cr1, cr0, 0	\n"
+		"isb	sy			\n"
+		:"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+	static const struct reg_config pfc_with_unlock[] = {
+		{ 0x0090, 0x00000000 },
+		{ 0x0094, 0x00000000 },
+		{ 0x0098, 0xc0000000 },
+		{ 0x0020, 0x00000000 },
+		{ 0x0024, 0x00000000 },
+		{ 0x0028, 0x00000000 },
+		{ 0x002c, 0x20000000 },
+		{ 0x0030, 0x00001249 },
+		{ 0x0034, 0x00000278 },
+		{ 0x0038, 0x00000841 },
+		{ 0x003c, 0x00000000 },
+		{ 0x0040, 0x00000000 },
+		{ 0x0044, 0x10000000 },
+		{ 0x0048, 0x00000001 },
+		{ 0x004c, 0x0004aab0 },
+		{ 0x0050, 0x37301b00 },
+		{ 0x0054, 0x00048da3 },
+		{ 0x0058, 0x089044a1 },
+		{ 0x005c, 0x2a3a55b4 },
+		{ 0x0160, 0x00000003 },
+		{ 0x0004, 0xffffffff },
+		{ 0x0008, 0x2aef3fff },
+		{ 0x000c, 0x3fffffff },
+		{ 0x0010, 0xff7fc07f },
+		{ 0x0014, 0x7f3ff3f8 },
+		{ 0x0018, 0x1cfdfff7 },
+	};
+
+	static const struct reg_config pfc_without_unlock[] = {
+		{ 0x0100, 0x1fffffff },
+		{ 0x0104, 0xffff0318 },
+		{ 0x0108, 0x387fffe1 },
+		{ 0x010c, 0x00803f80 },
+		{ 0x0110, 0x1520009f },
+		{ 0x0114, 0x00000000 },
+		{ 0x0118, 0x00000000 },
+	};
+
+	static const u32 pfc_base = 0xe6060000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+		writel(~pfc_with_unlock[i].val, pfc_base);
+		writel(pfc_with_unlock[i].val,
+		       pfc_base | pfc_with_unlock[i].off);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+		writel(pfc_without_unlock[i].val,
+		       pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+	static const u16 gpio_offs[] = {
+		0x1000, 0x3000, 0x4000, 0x5000
+	};
+
+	static const struct reg_config gpio_set[] = {
+		{ 0x4000, 0x00c00000 },
+		{ 0x5000, 0x63020000 },
+	};
+
+	static const struct reg_config gpio_clr[] = {
+		{ 0x1000, 0x00000000 },
+		{ 0x3000, 0x00000000 },
+		{ 0x4000, 0x00c00000 },
+		{ 0x5000, 0xe3020000 },
+	};
+
+	static const u32 gpio_base = 0xe6050000;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+		writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+		writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+	for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+		writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+	static const struct reg_config lbsc_config[] = {
+		{ 0x00, 0x00000020 },
+		{ 0x08, 0x00002020 },
+		{ 0x30, 0x02150326 },
+		{ 0x38, 0x077f077f },
+	};
+
+	static const u16 lbsc_offs[] = {
+		0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+	};
+
+	static const u32 lbsc_base = 0xfec00200;
+
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+		writel(lbsc_config[i].val,
+		       lbsc_base | lbsc_config[i].off);
+		writel(lbsc_config[i].val,
+		       lbsc_base | (lbsc_config[i].off + 4));
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+		writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+	static const struct reg_config dbsc_config1[] = {
+		{ 0x0018, 0x21000000 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0018, 0x10000000 },
+		{ 0x0280, 0x0000a55a },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x80000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config4[] = {
+		{ 0x0290, 0x00000010 },
+		{ 0x02a0, 0xf004649b },
+		{ 0x0290, 0x0000000f },
+		{ 0x02a0, 0x00181ee4 },
+		{ 0x0290, 0x00000060 },
+		{ 0x02a0, 0x330657b2 },
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000071 },
+		{ 0x0020, 0x00000007 },
+		{ 0x0024, 0x10030a02 },
+		{ 0x0030, 0x00000001 },
+		{ 0x00b0, 0x00000000 },
+		{ 0x0040, 0x0000000b },
+		{ 0x0044, 0x00000008 },
+		{ 0x0048, 0x00000000 },
+		{ 0x0050, 0x0000000b },
+		{ 0x0054, 0x000c000b },
+		{ 0x0058, 0x00000027 },
+		{ 0x005c, 0x0000001c },
+		{ 0x0060, 0x00000005 },
+		{ 0x0064, 0x00000018 },
+		{ 0x0068, 0x00000008 },
+		{ 0x006c, 0x0000000c },
+		{ 0x0070, 0x00000009 },
+		{ 0x0074, 0x00000012 },
+		{ 0x0078, 0x000000d0 },
+		{ 0x007c, 0x00140005 },
+		{ 0x0080, 0x00050004 },
+		{ 0x0084, 0x70233005 },
+		{ 0x0088, 0x000c0000 },
+		{ 0x008c, 0x00000300 },
+		{ 0x0090, 0x00000040 },
+		{ 0x0100, 0x00000001 },
+		{ 0x00c0, 0x00020001 },
+		{ 0x00c8, 0x20082008 },
+		{ 0x0380, 0x00020002 },
+		{ 0x0390, 0x0000000f },
+	};
+
+	static const struct reg_config dbsc_config5[] = {
+		{ 0x0244, 0x00000011 },
+		{ 0x0290, 0x00000006 },
+		{ 0x02a0, 0x0005c000 },
+		{ 0x0290, 0x00000003 },
+		{ 0x02a0, 0x0300c481 },
+		{ 0x0290, 0x00000023 },
+		{ 0x02a0, 0x00fdb6c0 },
+		{ 0x0290, 0x00000011 },
+		{ 0x02a0, 0x1000040b },
+		{ 0x0290, 0x00000012 },
+		{ 0x02a0, 0x9d5cbb66 },
+		{ 0x0290, 0x00000013 },
+		{ 0x02a0, 0x1a868300 },
+		{ 0x0290, 0x00000014 },
+		{ 0x02a0, 0x300214d8 },
+		{ 0x0290, 0x00000015 },
+		{ 0x02a0, 0x00000d70 },
+		{ 0x0290, 0x00000016 },
+		{ 0x02a0, 0x00000006 },
+		{ 0x0290, 0x00000017 },
+		{ 0x02a0, 0x00000018 },
+		{ 0x0290, 0x0000001a },
+		{ 0x02a0, 0x910035c7 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config6[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x00000181 },
+		{ 0x0018, 0x11000000 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config7[] = {
+		{ 0x0290, 0x00000001 },
+		{ 0x02a0, 0x0000fe01 },
+		{ 0x0290, 0x00000004 },
+	};
+
+	static const struct reg_config dbsc_config8[] = {
+		{ 0x0304, 0x00000000 },
+		{ 0x00f4, 0x01004c20 },
+		{ 0x00f8, 0x014000aa },
+		{ 0x00e0, 0x00000140 },
+		{ 0x00e4, 0x00081860 },
+		{ 0x00e8, 0x00010000 },
+		{ 0x0014, 0x00000001 },
+		{ 0x0010, 0x00000001 },
+		{ 0x0280, 0x00000000 },
+	};
+
+	static const u32 dbsc3_0_base = DBSC3_0_BASE;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+		writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+		writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+	dbsc_wait(0x240);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+		writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+		writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+		writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+	dbsc_wait(0x2a0);
+
+	for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+		writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	static const u32 qspi_base = 0xe6b10000;
+
+	writeb(0x08, qspi_base + 0x00);
+	writeb(0x00, qspi_base + 0x01);
+	writeb(0x06, qspi_base + 0x02);
+	writeb(0x01, qspi_base + 0x0a);
+	writeb(0x00, qspi_base + 0x0b);
+	writeb(0x00, qspi_base + 0x0c);
+	writeb(0x00, qspi_base + 0x0d);
+	writeb(0x00, qspi_base + 0x0e);
+
+	writew(0xe080, qspi_base + 0x10);
+
+	writeb(0xc0, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x18);
+	writeb(0x00, qspi_base + 0x08);
+	writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	/*
+	 * SD0 clock is set to 97.5MHz by default.
+	 * Set SD2 to the 97.5MHz as well.
+	 */
+	writel(SD_97500KHZ, SD2CKCR);
+
+	spl_init_sys();
+	spl_init_pfc();
+	spl_init_gpio();
+	spl_init_lbsc();
+	spl_init_dbsc();
+	spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const u32 jtag_magic = 0x1337c0de;
+	const u32 load_magic = 0xb33fc0de;
+
+	/*
+	 * If JTAG probe sets special word at 0xe6300020, then it must
+	 * put U-Boot into RAM and SPL will start it from RAM.
+	 */
+	if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+		printf("JTAG boot detected!\n");
+
+		while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+			;
+
+		spl_boot_list[0] = BOOT_DEVICE_RAM;
+		spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+		return;
+	}
+
+	/* Boot from SPI NOR with YMODEM UART fallback. */
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	spl_boot_list[1] = BOOT_DEVICE_UART;
+	spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 86fab8c..17fc8ae 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -1,17 +1,37 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE8080000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_R8A7790=y
 CONFIG_TARGET_LAGER=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SDRAM=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
@@ -19,22 +39,43 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
 CONFIG_SH_MMCIF=y
+CONFIG_RENESAS_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
 CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 97f7b2c..3bd4d51 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -15,14 +15,9 @@
 
 #include "rcar-gen2-common.h"
 
-/* STACK */
-#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR		0xB003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR		0xE827FFFC
-#endif
-#define STACK_AREA_SIZE			0xC000
-#define LOW_LEVEL_MERAM_STACK	\
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
 		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
 
 /* MEMORY */
@@ -32,60 +27,38 @@
 
 /* SCIF */
 
-/* SPI */
+/* FLASH */
 #define CONFIG_SPI
 
 /* SH Ether */
 #define CONFIG_SH_ETHER_USE_PORT	0
 #define CONFIG_SH_ETHER_PHY_ADDR	0x1
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_RCAR
-#define CONFIG_SYS_RCAR_I2C0_SPEED	400000
-#define CONFIG_SYS_RCAR_I2C1_SPEED	400000
-#define CONFIG_SYS_RCAR_I2C2_SPEED	400000
-#define CONFIG_SYS_RCAR_I2C3_SPEED	400000
-#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
 /* Board Clock */
 #define RMOBILE_XTAL_CLK	20000000u
 #define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
-#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
-#define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
 
 #define CONFIG_SYS_TMU_CLK_DIV	4
 
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	3
-
-/* MMC */
-#define CONFIG_SH_MMCIF_ADDR		0xEE220000
-#define CONFIG_SH_MMCIF_CLK		97500000
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA	0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA	0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA	0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA	0x00200000
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ	97500000
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0xffffffff\0"		\
+	"initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE		0xe6300000
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
 
 #endif	/* __LAGER_H */