* Patch by Fred Klatt, 25 Jun 2004:

  Add support for WindRiver's SBC8560 board

* Patch by Nicolas Lacressonniere, 24 Jun 2004
  Small Bugs fixes for "at91rm9200dk" board:
  - Timing modifications for SPI DataFlash access
  - Fix NAND flash detection bug

* Patch by Nicolas Lacressonniere, 24 Jun 2004:
  Add Support for Flash AT49BV6416 for AT91RM9200DK board

20 files changed, 1505 insertions, 122 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 33fafcb..5e6468e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,17 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Patch by Fred Klatt, 25 Jun 2004:
+  Add support for WindRiver's SBC8560 board
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004
+  Small Bugs fixes for "at91rm9200dk" board:
+  - Timing modifications for SPI DataFlash access
+  - Fix NAND flash detection bug
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004:
+  Add Support for Flash AT49BV6416 for AT91RM9200DK board
+
 * Patch by Jon Loeliger, 17 June 2004:
   Completion of the 8540ADS/8560ADS updates:
   Fix some PCI and Rapid I/O memory maps,
diff --git a/MAKEALL b/MAKEALL
index d35042f..a0ae785 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -98,7 +98,7 @@ LIST_8260="	\
 #########################################################################
 
 LIST_85xx="	\
-	MPC8540ADS	MPC8560ADS	stxgp3				\
+	MPC8540ADS	MPC8560ADS	SBC8560		stxgp3		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 26dddb9..516ae69 100644
--- a/Makefile
+++ b/Makefile
@@ -1010,6 +1010,17 @@ MPC8560ADS_config:	unconfig
 stxgp3_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
 
+SBC8560_33_config \
+SBC8560_66_config:      unconfig
+	@if [ "$(findstring _66_,$@)" ] ; then \
+		echo "#define CONFIG_PCI_66"  >>include/config.h ; \
+		echo "... 66 MHz PCI" ; \
+	else \
+		>include/config.h ; \
+		echo "... 33 MHz PCI" ; \
+	fi
+	@./mkconfig -a SBC8560 ppc mpc85xx sbc8560
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
diff --git a/README b/README
index faa5ec4..8b545f8 100644
--- a/README
+++ b/README
@@ -269,24 +269,24 @@ The following options need to be configured:
 		CONFIG_CSB272		CONFIG_JSE		CONFIG_Sandpoint8240
 		CONFIG_CU824		CONFIG_LANTEC		CONFIG_Sandpoint8245
 		CONFIG_DASA_SIM		CONFIG_lwmon		CONFIG_sbc8260
-		CONFIG_DB64360		CONFIG_MBX		CONFIG_SM850
-		CONFIG_DB64460		CONFIG_MBX860T		CONFIG_SPD823TS
-		CONFIG_DU405		CONFIG_MHPC		CONFIG_STXGP3
-		CONFIG_DUET_ADS		CONFIG_MIP405		CONFIG_SXNI855T
-		CONFIG_EBONY		CONFIG_MOUSSE		CONFIG_TQM823L
-		CONFIG_ELPPC		CONFIG_MPC8260ADS	CONFIG_TQM8260
-		CONFIG_ELPT860		CONFIG_MPC8540ADS	CONFIG_TQM850L
-		CONFIG_ep8260		CONFIG_MPC8560ADS	CONFIG_TQM855L
-		CONFIG_ERIC		CONFIG_MUSENKI		CONFIG_TQM860L
-		CONFIG_ESTEEM192E	CONFIG_MVS1		CONFIG_TTTech
-		CONFIG_ETX094		CONFIG_NETPHONE		CONFIG_UTX8245
-		CONFIG_EVB64260		CONFIG_NETTA		CONFIG_V37
-		CONFIG_FADS823		CONFIG_NETVIA		CONFIG_W7OLMC
-		CONFIG_FADS850SAR	CONFIG_NX823		CONFIG_W7OLMG
-		CONFIG_FADS860T		CONFIG_OCRTC		CONFIG_WALNUT405
-		CONFIG_FLAGADM		CONFIG_ORSG		CONFIG_ZPC1900
-		CONFIG_FPS850L		CONFIG_OXC		CONFIG_ZUMA
-		CONFIG_FPS860L
+		CONFIG_DB64360		CONFIG_MBX		CONFIG_sbc8560
+		CONFIG_DB64460		CONFIG_MBX860T		CONFIG_SM850
+		CONFIG_DU405		CONFIG_MHPC		CONFIG_SPD823TS
+		CONFIG_DUET_ADS		CONFIG_MIP405		CONFIG_STXGP3
+		CONFIG_EBONY		CONFIG_MOUSSE		CONFIG_SXNI855T
+		CONFIG_ELPPC		CONFIG_MPC8260ADS	CONFIG_TQM823L
+		CONFIG_ELPT860		CONFIG_MPC8540ADS	CONFIG_TQM8260
+		CONFIG_ep8260		CONFIG_MPC8560ADS	CONFIG_TQM850L
+		CONFIG_ERIC		CONFIG_MUSENKI		CONFIG_TQM855L
+		CONFIG_ESTEEM192E	CONFIG_MVS1		CONFIG_TQM860L
+		CONFIG_ETX094		CONFIG_NETPHONE		CONFIG_TTTech
+		CONFIG_EVB64260		CONFIG_NETTA		CONFIG_UTX8245
+		CONFIG_FADS823		CONFIG_NETVIA		CONFIG_V37
+		CONFIG_FADS850SAR	CONFIG_NX823		CONFIG_W7OLMC
+		CONFIG_FADS860T		CONFIG_OCRTC		CONFIG_W7OLMG
+		CONFIG_FLAGADM		CONFIG_ORSG		CONFIG_WALNUT405
+		CONFIG_FPS850L		CONFIG_OXC		CONFIG_ZPC1900
+		CONFIG_FPS860L					CONFIG_ZUMA
 
 		ARM based boards:
 		-----------------
@@ -2091,16 +2091,18 @@ configurations; the following names are supported:
 	CPCI405_config		JSE_config		rsdproto_config
 	CPCIISER4_config	LANTEC_config		Sandpoint8240_config
 	csb272_config		lwmon_config		sbc8260_config
-	CU824_config		MBX860T_config		SM850_config
-	DUET_ADS_config		MBX_config		SPD823TS_config
-	EBONY_config		MPC8260ADS_config	stxgp3_config
-	ELPT860_config		MPC8540ADS_config	SXNI855T_config
-	ESTEEM192E_config	MPC8560ADS_config	TQM823L_config
-	ETX094_config		NETVIA_config		TQM850L_config
-	FADS823_config		omap1510inn_config	TQM855L_config
-	FADS850SAR_config	omap1610h2_config	TQM860L_config
-	FADS860T_config		omap1610inn_config	WALNUT405_config
-	FPS850L_config		omap5912osk_config	ZPC1900_config
+	CU824_config		MBX860T_config		SBC8560_33_config
+	DUET_ADS_config		MBX_config		SBC8560_66_config
+	EBONY_config		MPC8260ADS_config	SM850_config
+	ELPT860_config		MPC8540ADS_config	SPD823TS_config
+	ESTEEM192E_config	MPC8560ADS_config	stxgp3_config
+	ETX094_config		NETVIA_config		SXNI855T_config
+	FADS823_config		omap1510inn_config	TQM823L_config
+	FADS850SAR_config	omap1610h2_config	TQM850L_config
+	FADS860T_config		omap1610inn_config	TQM855L_config
+	FPS850L_config		omap5912osk_config	TQM860L_config
+							WALNUT405_config
+							ZPC1900_config
 
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for
diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c
index 8a05c53..606ea48 100644
--- a/board/at91rm9200dk/at91rm9200dk.c
+++ b/board/at91rm9200dk/at91rm9200dk.c
@@ -102,6 +102,10 @@ void nand_init (void)
 	*AT91C_PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
 	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
 
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
 	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
 		printf ("  No SmartMedia card inserted\n");
 #ifdef DEBUG
diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c
index 9a67755..5220fcf 100644
--- a/board/at91rm9200dk/flash.c
+++ b/board/at91rm9200dk/flash.c
@@ -42,20 +42,22 @@ typedef struct OrgDef
 /* Flash Organizations */
 OrgDef OrgAT49BV16x4[] =
 {
-	{ 8, 8*1024 }, /* 8 * 8kBytes sectors */
-	{ 2, 32*1024 }, /* 2 * 32kBytes sectors */
-	{ 30, 64*1024 } /* 30 * 64kBytes sectors */
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{  2, 32*1024 },	/*   2 * 32 kBytes sectors */
+	{ 30, 64*1024 },	/*  30 * 64 kBytes sectors */
 };
 
 OrgDef OrgAT49BV16x4A[] =
 {
-	{ 8, 8*1024 }, /* 8 * 8kBytes sectors */
-	{ 31, 64*1024 } /* 31 * 64kBytes sectors */
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 31, 64*1024 },	/*  31 * 64 kBytes sectors */
 };
 
-
-#define FLASH_BANK_SIZE 0x200000	/* 2 MB */
-#define MAIN_SECT_SIZE  0x10000		/* 64 KB */
+OrgDef OrgAT49BV6416[] =
+{
+	{   8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 127, 64*1024 },	/* 127 * 64 kBytes sectors */
+};
 
 flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
 
@@ -73,13 +75,11 @@ flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
 #define CMD_ERASE_CONFIRM	0x0030
 #define CMD_PROGRAM		0x00A0
 #define CMD_UNLOCK_BYPASS	0x0020
+#define CMD_SECTOR_UNLOCK	0x0070
 
 #define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1)))
 #define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1)))
 
-#define IDENT_FLASH_ADDR1	(*(volatile u16 *)(CFG_FLASH_BASE + (0x0000555<<1)))
-#define IDENT_FLASH_ADDR2	(*(volatile u16 *)(CFG_FLASH_BASE + (0x0000AAA<<1)))
-
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080
 #define BIT_PROGRAM_ERROR	0x0020
@@ -95,17 +95,17 @@ void flash_identification (flash_info_t * info)
 {
 	volatile u16 manuf_code, device_code, add_device_code;
 
-	IDENT_FLASH_ADDR1 = FLASH_CODE1;
-	IDENT_FLASH_ADDR2 = FLASH_CODE2;
-	IDENT_FLASH_ADDR1 = ID_IN_CODE;
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_IN_CODE;
 
 	manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
 	device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
 	add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));
 
-	IDENT_FLASH_ADDR1 = FLASH_CODE1;
-	IDENT_FLASH_ADDR2 = FLASH_CODE2;
-	IDENT_FLASH_ADDR1 = ID_OUT_CODE;
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_OUT_CODE;
 
 	/* Vendor type */
 	info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
@@ -117,14 +117,36 @@ void flash_identification (flash_info_t * info)
 			(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
 			info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
 			printf ("AT49BV1614A (16Mbit)\n");
+		} else {				/* AT49BV1614 Flash */
+			info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
+			printf ("AT49BV1614 (16Mbit)\n");
 		}
 
-	} else {				/* AT49BV1614 Flash */
-		info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
-		printf ("AT49BV1614 (16Mbit)\n");
+	} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
+		info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
+		printf ("AT49BV6416 (64Mbit)\n");
 	}
 }
 
+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
+{
+	int i, nb_sectors = 0;
+
+	for (i=0; i<nb_blocks; i++){
+		nb_sectors += pOrgDef[i].sector_number;
+	}
+
+	return nb_sectors;
+}
+
+void flash_unlock_sector(flash_info_t * info, unsigned int sector)
+{
+	volatile u16 *addr = (volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	*addr = CMD_SECTOR_UNLOCK;
+}
+
 
 ulong flash_init (void)
 {
@@ -140,23 +162,29 @@ ulong flash_init (void)
 
 		flash_identification (&flash_info[i]);
 
-		flash_info[i].size = FLASH_BANK_SIZE;
-
 		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
 			(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
 
 			pOrgDef = OrgAT49BV16x4;
 			flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
-		} else {			/* AT49BV1614A Flash */
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT - 1;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT - 1);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)){	/* AT49BV1614A Flash */
 
 			pOrgDef = OrgAT49BV16x4A;
 			flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			pOrgDef = OrgAT49BV6416;
+			flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
+		} else {
+			flash_nb_blocks = 0;
+			pOrgDef = OrgAT49BV16x4;
 		}
 
+		flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
+		memset (flash_info[i].protect, 0, flash_info[i].sector_count);
+
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -164,15 +192,26 @@ ulong flash_init (void)
 
 		sector = 0;
 		start_address = flashbase;
+		flash_info[i].size = 0;
 
 		for (j = 0; j < flash_nb_blocks; j++) {
 			for (k = 0; k < pOrgDef[j].sector_number; k++) {
 				flash_info[i].start[sector++] = start_address;
 				start_address += pOrgDef[j].sector_size;
+				flash_info[i].size += pOrgDef[j].sector_size;
 			}
 		}
 
 		size += flash_info[i].size;
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			/* Unlock all sectors at reset */
+			for (j=0; j<flash_info[i].sector_count; j++){
+				flash_unlock_sector(&flash_info[i], j);
+			}
+		}
 	}
 
 	/* Protect binary boot image */
@@ -215,6 +254,9 @@ void flash_print_info (flash_info_t * info)
 	case (ATM_ID_BV1614A & FLASH_TYPEMASK):
 		printf ("AT49BV1614A (16Mbit)\n");
 		break;
+	case (ATM_ID_BV6416 & FLASH_TYPEMASK):
+		printf ("AT49BV6416 (64Mbit)\n");
+		break;
 	default:
 		printf ("Unknown Chip Type\n");
 		goto Done;
@@ -234,7 +276,7 @@ void flash_print_info (flash_info_t * info)
 	}
 	printf ("\n");
 
-  Done:
+Done:	;
 }
 
 /*-----------------------------------------------------------------------
diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile
new file mode 100644
index 0000000..da295fb
--- /dev/null
+++ b/board/sbc8560/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8560 board
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sbc8560/config.mk b/board/sbc8560/config.mk
new file mode 100644
index 0000000..c025a0e
--- /dev/null
+++ b/board/sbc8560/config.mk
@@ -0,0 +1,35 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8560 board
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# based on mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 256K
+#
+TEXT_BASE = 0xfffc0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S
new file mode 100644
index 0000000..3d8d180
--- /dev/null
+++ b/board/sbc8560/init.S
@@ -0,0 +1,165 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+* Added support for Wind River SBC8560 board
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(512M) -or- larger
+ * c000_0000-cfff_ffff: PCI(256M)
+ * d000_0000-dfff_ffff: RapidIO(256M)
+ * e000_0000-ffff_ffff: localbus(512M)
+ *   e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
+ *   e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
+ *   e800_0000-efff_ffff: LBC 128M, nothing here
+ *   f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
+ *   f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
+ *   f800_0000-fdff_ffff: LBC 64M, nothing here
+ *   fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
+ *   fd00_0000-fdff_ffff: LBC 16M, nothing here
+ *   fe00_0000-feff_ffff: LBC 16M, nothing here
+ *   ff00_0000-ff6f_ffff: LBC 7M, nothing here
+ *   ff70_0000-ff7f_ffff: CCSRBAR 1M
+ *   ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+  #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+  #define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#else
+  #define LAWBAR0 0
+  #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR2 ((0xe0000000>>12) & 0xfffff)
+#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+	.section .bootpg, "ax"
+	.globl  law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl		tlb1_entry
+
+tlb1_entry:
+	entry_start
+
+	.long 0x08	/* the following data table uses a few of 16 TLB entries */
+
+/* TLB for CCSRBAR (IMMR) */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+/* TLB for Local Bus stuff, just map the whole 512M */
+/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
+
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+#else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+#endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+#ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+#else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+#endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+#else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+#endif
+	entry_end
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
new file mode 100644
index 0000000..a784e34
--- /dev/null
+++ b/board/sbc8560/sbc8560.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
+	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+	volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
+#endif
+	/* reset Giga bit Ethernet port if needed here */
+
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr[0] &= ~0x20;
+	udelay(2);
+	bcsr[0] |= 0x20;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr[0] &= ~0x10;
+	udelay(2);
+	bcsr[0] |= 0x10;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	miiphy_reset(0x0);	/* reset PHY */
+	miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
+	miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: Wind River SBC8560 Board\n");
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if XXX
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+
+#define CFG_DDR_CONTROL 0xc2000000
+
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds		= 0x00000007;
+	ddr->cs1_bnds		= 0x0010001f;
+	ddr->cs2_bnds		= 0x00000000;
+	ddr->cs3_bnds		= 0x00000000;
+	ddr->cs0_config		= 0x80000102;
+	ddr->cs1_config		= 0x80000102;
+	ddr->cs2_config		= 0x00000000;
+	ddr->cs3_config		= 0x00000000;
+	ddr->timing_cfg_1	= 0x37334321;
+	ddr->timing_cfg_2	= 0x00000800;
+	ddr->sdram_cfg		= 0x42000000;
+	ddr->sdram_mode		= 0x00000022;
+	ddr->sdram_interval	= 0x05200100;
+	ddr->err_sbe		= 0x00ff0000;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds
new file mode 100644
index 0000000..a3ed1d5
--- /dev/null
+++ b/board/sbc8560/u-boot.lds
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/sbc8560/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/sbc8560/init.o (.text)
+    cpu/mpc85xx/commproc.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/serial_scc.o (.text)
+    cpu/mpc85xx/ether_fcc.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/i2c.o (.text)
+    cpu/mpc85xx/spd_sdram.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 8d115eb..c874e7c 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -20,6 +20,10 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
+#ifdef CONFIG_AT91RM9200DK
+#include <asm/arch/hardware.h>
+#endif
+
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ids.h>
 #include <jffs2/jffs2.h>
diff --git a/cpu/at91rm9200/at45.c b/cpu/at91rm9200/at45.c
index 9dfe560..3c00132 100644
--- a/cpu/at91rm9200/at45.c
+++ b/cpu/at91rm9200/at45.c
@@ -25,7 +25,14 @@
 #ifdef CONFIG_HAS_DATAFLASH
 #include <dataflash.h>
 
-#define SPI_CLK 5000000
+#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xC << 16)
+#define DATAFLASH_TCHS	(0x1 << 24)
+
 #define AT91C_TIMEOUT_WRDY			200000
 #define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
 #define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
@@ -50,9 +57,11 @@ void AT91F_SpiInit(void) {
 	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
 
 	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8);
+	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
 
-	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8);
+	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
 
 }
 
diff --git a/cpu/mpc85xx/tsec.c b/cpu/mpc85xx/tsec.c
index 0d858ed..3255db8 100644
--- a/cpu/mpc85xx/tsec.c
+++ b/cpu/mpc85xx/tsec.c
@@ -25,13 +25,6 @@
 
 #define TX_BUF_CNT 2
 
-#undef TSEC_DEBUG
-#ifdef TSEC_DEBUG
-#define DBGPRINT(x,y) printf(x,y)
-#else
-#define DBGPRINT(x,y)
-#endif
-
 static uint rxIdx;	/* index of the current RX buffer */
 static uint txIdx;	/* index of the current TX buffer */
 
@@ -564,7 +557,7 @@ static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
 	/* Find an empty buffer descriptor */
 	for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 		if (i >= TOUT_LOOP) {
-			DBGPRINT("%s: tsec: tx buffers full\n", dev->name);
+			debug ("%s: tsec: tx buffers full\n", dev->name);
 			return result;
 		}
 	}
@@ -579,7 +572,7 @@ static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
 	/* Wait for buffer to be transmitted */
 	for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 		if (i >= TOUT_LOOP) {
-			DBGPRINT("%s: tsec: tx error\n", dev->name);
+			debug ("%s: tsec: tx error\n", dev->name);
 			return result;
 		}
 	}
diff --git a/doc/README.sbc8560 b/doc/README.sbc8560
new file mode 100644
index 0000000..52592e3
--- /dev/null
+++ b/doc/README.sbc8560
@@ -0,0 +1,53 @@
+The port was tested on Wind River System Sbc8560 board <www.windriver.com>.
+U-Boot was installed on the flash memory of the CPU card (no the SODIMM).
+
+NOTE: Please configure uboot compile to the proper PCI frequency and
+setup the appropriate DIP switch settings.
+
+SBC8560 board:
+
+Make sure boards switches are set to their appropriate conditions.
+Refer to the Engineering Reference Guide ERG-00300-002. Of particular
+importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which
+select the on-board FLASH device (Intel 28F128Jx); 2) The settings
+for the Clock SW9 (33 MHz or 66 MHz).
+
+	Note:	SW9 Settings: 66 MHz
+		4:1 ratio CCB clocks:SYSCLK
+		3:1 ration e500 Core:CCB
+		pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on
+	Note:	SW9 Settings: 33 MHz
+		8:1 ratio CCB clocks:SYSCLK
+		3:1 ration e500 Core:CCB
+		pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on
+
+
+Flashing the FLASH device with the "Wind River ICE":
+
+1) Properly connect and configure the Wind River ICE to the
+   target JTAG port. This includes running the SBC8560 register script.
+   Make sure target memory can be read and written.
+
+2) Build the u-boot image:
+	make distclean
+	make SBC8560_66_config or SBC8560_33_config
+	make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
+
+   Note: reference is made to the ELDK3.0 compiler but any 85xx cross-compiler
+	 should suffice.
+
+3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter).
+   The bin file should be converted from fffc0000 to ffffffff
+
+4) Setup the Flash Utility (tools menu) for:
+
+   Determine the clock speed of the PCI bus and set SW9 accordingly
+	Note: the speed of the PCI bus defaults to the slowest PCI card
+   PlayBack the "default" register file for the SBC8560
+   Select the uboot.bin file with zero bias
+   Select the initialize Target prior to programming
+   Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm
+   Select the erase base address from FFFC0000 to FFFFFFFF
+   Select the start address from 0 with size of 4000
+
+5) Erase and Program
diff --git a/examples/Makefile b/examples/Makefile
index 3229303..e94ac47 100644
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000
+# (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 60f1737..29ed49d 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -459,6 +459,8 @@ typedef struct _AT91S_PDC {
 #define AT91C_ID_TC0    ((unsigned int) 17) /* Timer Counter 0 */
 #define AT91C_ID_EMAC   ((unsigned int) 24) /* Ethernet MAC */
 #define AT91C_ID_SPI    ((unsigned int) 13) /* Serial Peripheral Interface */
+#define AT91C_ID_PIOB	((unsigned int) 3)
+#define AT91C_ID_PIOC	((unsigned int) 4)
 
 #define AT91C_PIO_PC1        ((unsigned int) 1 <<  1) /* Pin Controlled by PC1 */
 #define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /*  Burst Flash Ready */
diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h
new file mode 100644
index 0000000..cf5ef63
--- /dev/null
+++ b/include/configs/SBC8560.h
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE			*/
+#define CONFIG_E500		1	/* BOOKE e500 family		*/
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
+#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
+
+
+#define CONFIG_MPC8560		1	/* MPC8560 specific		*/
+#define CONFIG_SBC8560		1	/* configuration for SBC8560 board */
+
+/* XXX flagging this as something I might want to delete */
+#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific	*/
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
+#undef	CONFIG_PCI			/* pci ethernet support		*/
+#undef  CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/
+
+
+#define CONFIG_ENV_OVERWRITE
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you need a flash-boot image(u-boot.bin), if so undef this.
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+#if defined(CONFIG_PCI_66)		/* some PCI card is 33Mhz only	*/
+  #define CONFIG_SYS_CLK_FREQ	66000000/* sysclk for MPC85xx		*/
+#else
+  #define CONFIG_SYS_CLK_FREQ	33000000/* most pci cards are 33Mhz	*/
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
+#undef	CONFIG_BTB			    /* toggle branch predition	*/
+#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+
+#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00200000  /* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
+     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
+     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
+#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+
+#if XXX
+  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
+#else
+  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
+#endif
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
+#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
+
+#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
+#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+
+#if defined(CONFIG_MPC85xx_REV1)
+  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
+  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
+  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
+#else /* Boot from real Flash */
+  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
+  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
+  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
+  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
+#endif
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+
+/* local bus definitions */
+#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
+#define CFG_OR1_PRELIM		0xfc000ff7
+
+#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
+#define CFG_OR2_PRELIM		0x00000000
+
+#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
+#define CFG_OR3_PRELIM		0xfc000cc1
+
+#if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
+#else
+  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
+#endif
+#define CFG_OR4_PRELIM		0xfc000cc1
+
+#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
+#if 1
+  #define CFG_OR5_PRELIM	0xff000ff7
+#else
+  #define CFG_OR5_PRELIM	0xff0000f0
+#endif
+
+#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
+#define CFG_OR6_PRELIM		0xfc000ff7
+#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+/* just hijack the MOT BCSR def for SBC8560 misc devices */
+#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
+/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
+#undef	CONFIG_CONS_NONE			/* define if console on something else */
+
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
+#define CONFIG_BAUDRATE		9600
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
+#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+
+#define CFG_PCI_MEM_BASE	0xC0000000
+#define CFG_PCI_MEM_PHYS	0xC0000000
+#define CFG_PCI_MEM_SIZE	0x10000000
+
+#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
+
+  #define CONFIG_NET_MULTI	1
+  #define CONFIG_PHY_BCM5421S	1	/* GigaBit Ether PHY	     */
+  #define CONFIG_MII		1	/* MII PHY management		*/
+  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+  #undef  CONFIG_ETHER_NONE		/* define if ether on something else */
+  #define CONFIG_ETHER_ON_FCC2		/* cpm FCC ethernet support	*/
+  #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
+
+  #if (CONFIG_ETHER_INDEX == 2)
+    /*
+     * - Rx-CLK is CLK13
+     * - Tx-CLK is CLK14
+     * - Select bus for bd/buffers
+     * - Full duplex
+     */
+    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+    #define CFG_CPMFCR_RAMTYPE	0
+    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)
+
+  #elif (CONFIG_ETHER_INDEX == 3)
+    /* need more definitions here for FE3 */
+  #endif				/* CONFIG_ETHER_INDEX */
+
+  #define CONFIG_MII			/* MII PHY management */
+  #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+  /*
+   * GPIO pins used for bit-banged MII communications
+   */
+  #define MDIO_PORT	2		/* Port C */
+  #define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+  #define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+  #define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+  #define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+  #define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+  #define MIIDELAY	udelay(1)
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#if 0
+#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
+#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
+#endif
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+
+#if 0
+/* XXX This doesn't work and I don't want to fix it */
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+  #define CFG_RAMBOOT
+#else
+  #undef  CFG_RAMBOOT
+#endif
+#endif
+
+/* Environment */
+#if !defined(CFG_RAMBOOT)
+  #if defined(CONFIG_RAM_AS_FLASH)
+    #define CFG_ENV_IS_NOWHERE
+    #define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
+    #define CFG_ENV_SIZE	0x2000
+  #else
+    #define CFG_ENV_IS_IN_FLASH	1
+    #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+    #define CFG_ENV_ADDR	(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+    #define CFG_ENV_SIZE	0x2000 /* CFG_ENV_SECT_SIZE */
+  #endif
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
+/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
+#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				 ~(CFG_CMD_ENV | \
+				  CFG_CMD_LOADS ))
+  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				~(CFG_CMD_ENV))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"SBC8560=> " /* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+  #define CONFIG_ETHADDR	00:01:af:07:9b:8a
+  #define CONFIG_ETH1ADDR	00:01:af:07:9b:8b
+  #define CONFIG_ETH2ADDR	00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP		192.168.0.131
+#define CONFIG_IPADDR		192.168.0.105
+#define CONFIG_GATEWAYIP	0.0.0.0
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_HOSTNAME		SBC8560
+#define CONFIG_ROOTPATH		/home/ppc
+#define CONFIG_BOOTFILE		pImage
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 3949f9c..94b6a8d 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -29,20 +29,20 @@
  * If we are developing, we might want to start armboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
-#define CONFIG_INIT_CRITICAL            /* undef for developing */
+#define CONFIG_INIT_CRITICAL		/* undef for developing */
 
 /* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK  179712000  /* from 18.432 MHz crystal (18432000 / 4 * 39) */
-#define AT91C_MASTER_CLOCK  59904000  /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
-/* #define AT91C_MASTER_CLOCK  44928000 */  /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
+#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
+#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+/* #define AT91C_MASTER_CLOCK	44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
 
-#define CONFIG_AT91RM9200DK	 1	/* on an AT91RM9200DK Board      */
+#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	 */
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
+#define CONFIG_INITRD_TAG	1
 
 /*
  * Size of malloc() pool
@@ -63,10 +63,10 @@
 #undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
 
 #define CONFIG_BOOTDELAY      3
-/* #define CONFIG_ENV_OVERWRITE  1 */
+/* #define CONFIG_ENV_OVERWRITE	1 */
 
 #define CONFIG_COMMANDS		\
-		       ((CONFIG_CMD_DFL	| \
+		       ((CONFIG_CMD_DFL | \
 			CFG_CMD_DHCP ) & \
 		      ~(CFG_CMD_BDI | \
 			CFG_CMD_IMI | \
@@ -85,12 +85,12 @@
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
-#define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
-#define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
+#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
 
 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
@@ -111,53 +111,53 @@
 #define PHYS_SDRAM 0x20000000
 #define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
 
-#define CFG_MEMTEST_START PHYS_SDRAM
-#define CFG_MEMTEST_END   CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
 #define CONFIG_DRIVER_ETHER
-#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
-#define CONFIG_HAS_DATAFLASH	1
-#define CFG_SPI_WRITE_TOUT	(5*CFG_HZ)
-#define CFG_MAX_DATAFLASH_BANKS 2
-#define CFG_MAX_DATAFLASH_PAGES 16384
+#define CONFIG_HAS_DATAFLASH		1
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 	2
+#define CFG_MAX_DATAFLASH_PAGES 	16384
 #define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
 #define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
 
-#define PHYS_FLASH_1 0x10000000
-#define PHYS_FLASH_SIZE 0x200000  /* 2 megs main flash */
-#define CFG_FLASH_BASE		PHYS_FLASH_1
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_MAX_FLASH_SECT 40
-#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x200000  /* 2 megs main flash */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		256
+#define CFG_FLASH_ERASE_TOUT		(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2*CFG_HZ) /* Timeout for Flash Write */
 
 #undef	CFG_ENV_IS_IN_DATAFLASH
 
 #ifdef CFG_ENV_IS_IN_DATAFLASH
-#define CFG_ENV_OFFSET 0x20000
-#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
-#define CFG_ENV_SIZE 0x2000  /* 0x8000 */
+#define CFG_ENV_OFFSET			0x20000
+#define CFG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
 #else
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000)  /* 0x10000 */
-#define CFG_ENV_SIZE 0x2000  /* 0x8000 */
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0xe000)  /* 0x10000 */
+#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
 #endif
 
 
-#define CFG_LOAD_ADDR 0x21000000  /* default load address */
+#define CFG_LOAD_ADDR		0x21000000  /* default load address */
 
 #define CFG_BOOT_SIZE		0x6000 /* 24 KBytes */
-#define CFG_U_BOOT_BASE 	(PHYS_FLASH_1 + 0x10000)
-#define CFG_U_BOOT_SIZE		0x10000	/* 64 KBytes */
+#define CFG_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
+#define CFG_U_BOOT_SIZE		0x10000 /* 64 KBytes */
 
-#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */
-#define	CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 
 #ifndef __ASSEMBLY__
 /*-----------------------------------------------------------------------
@@ -167,20 +167,19 @@
  * and can be used by the board specific code (eg board/...)
  */
 
-struct bd_info_ext
-{
-    /* helper variable for board environment handling
-     *
-     * env_crc_valid == 0    =>   uninitialised
-     * env_crc_valid  > 0    =>   environment crc in flash is valid
-     * env_crc_valid  < 0    =>   environment crc in flash is invalid
-     */
-     int	env_crc_valid;
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0    =>   uninitialised
+	 * env_crc_valid  > 0    =>   environment crc in flash is valid
+	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
 };
 #endif
 
-#define	CFG_HZ AT91C_MASTER_CLOCK/2  /* AT91C_TC0_CMR is implicitly set to
-					AT91C_TC_TIMER_DIV1_CLOCK */
+#define CFG_HZ AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
+					/* AT91C_TC_TIMER_DIV1_CLOCK */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/flash.h b/include/flash.h
index 51a7ae0..0b28da7 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -200,8 +200,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 
 #define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
 
-#define ATM_ID_BV1614	0x000000C0	/* 49BV1614 ID */
+#define ATM_ID_BV1614	0x000000C0	/* 49BV1614  ID */
 #define ATM_ID_BV1614A	0x000000C8	/* 49BV1614A ID */
+#define ATM_ID_BV6416	0x000000D6	/* 49BV6416  ID */
 
 #define FUJI_ID_29F800BA  0x22582258	/* MBM29F800BA ID  (8M) */
 #define FUJI_ID_29F800TA  0x22D622D6	/* MBM29F800TA ID  (8M) */