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| author | stroese <stroese> | 2003-03-20 15:27:41 +0000 |
|---|---|---|
| committer | stroese <stroese> | 2003-03-20 15:27:41 +0000 |
| commit | 97a43d641de267eb715888a6b8aba43f83327b93 (patch) | |
| tree | ddec29b26be1bb28e77251821a077033b1507c15 | |
| parent | 7e11d8269e4491cffd10ea0439c29585d766db77 (diff) | |
| download | u-boot-97a43d641de267eb715888a6b8aba43f83327b93.zip u-boot-97a43d641de267eb715888a6b8aba43f83327b93.tar.gz u-boot-97a43d641de267eb715888a6b8aba43f83327b93.tar.bz2 | |
Added edge conditioning register (ecr) for PPC405GPr.
| -rw-r--r-- | include/ppc405.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index e09e9f8..c99d591 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -236,6 +236,7 @@ #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#define ecr (0xAA) /* edge conditioning register (405GPr) */ /* Bit definitions */ #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ |