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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-07-19 10:13:23 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-07-25 08:47:52 +0900 |
| commit | 4a610fada193057c97c1b23016ef119f98459b22 (patch) | |
| tree | c4f4944dab0f70d722b0fe73de231ae873ef67ba | |
| parent | 0dc4addb9111a1587ba9c08594a0f087905a572a (diff) | |
| download | u-boot-4a610fada193057c97c1b23016ef119f98459b22.zip u-boot-4a610fada193057c97c1b23016ef119f98459b22.tar.gz u-boot-4a610fada193057c97c1b23016ef119f98459b22.tar.bz2 | |
mtd: nand: denali: correct buffer alignment for DMA transfer
The NAND framework makes sure to pass in the buffer with at least
chip->buf_align alignment. Currently, the Denali NAND driver only
requests 16 byte alignment. This causes unaligned cache operations
for the DMA transfer.
[Error Example]
=> nand read 81000010 0 1000
NAND read: device 0 offset 0x0, size 0x1000
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
4096 bytes read: OK
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| -rw-r--r-- | drivers/mtd/nand/denali.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 6266c8a..7302c37 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1270,7 +1270,7 @@ int denali_init(struct denali_nand_info *denali) denali->dma_avail = 1; if (denali->dma_avail) { - chip->buf_align = 16; + chip->buf_align = ARCH_DMA_MINALIGN; if (denali->caps & DENALI_CAP_DMA_64BIT) denali->setup_dma = denali_setup_dma64; else |