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| author | Chen-Yu Tsai <wens@csie.org> | 2017-09-22 15:26:33 +0800 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2017-11-10 19:10:33 +0530 |
| commit | 13ae2a40e7d458ad0c2961359c346578a305263d (patch) | |
| tree | 0675557c844bf8f686bb7a6d37d303e8a5230571 | |
| parent | 60567a320f4a55f05ae94fbb34f7aac0dd4c8fea (diff) | |
| download | u-boot-13ae2a40e7d458ad0c2961359c346578a305263d.zip u-boot-13ae2a40e7d458ad0c2961359c346578a305263d.tar.gz u-boot-13ae2a40e7d458ad0c2961359c346578a305263d.tar.bz2 | |
net: sun8i_emac: Fix build for non-H3/H5 SoCs
Only the H3/H5 SoCs have an internal PHY and its related clock and
reset controls.
Use an #ifdef to guard the internal PHY control code block so it
can be built for other SoCs, such as the A83T or A64.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
| -rw-r--r-- | drivers/net/sun8i_emac.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 09bbb2c..3ccc6b0 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -604,6 +604,8 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#ifdef CONFIG_MACH_SUNXI_H3_H5 + /* Only H3/H5 have clock controls for internal EPHY */ if (priv->use_internal_phy) { /* Set clock gating for ephy */ setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); @@ -611,6 +613,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) /* Deassert EPHY */ setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); } +#endif /* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); |