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| author | Johannes Schneider <johannes.schneider@leica-geosystems.com> | 2022-09-06 14:15:03 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-09-18 22:56:10 +0200 |
| commit | 25b7ce32871f94b96385b31e4bd6b1fd830cccd7 (patch) | |
| tree | e6bb272c0334fc1276020d80b080996058b2fbba | |
| parent | b7d29fd8a7b3502cfe1bcb86a897dae82ef6e49d (diff) | |
| download | u-boot-25b7ce32871f94b96385b31e4bd6b1fd830cccd7.zip u-boot-25b7ce32871f94b96385b31e4bd6b1fd830cccd7.tar.gz u-boot-25b7ce32871f94b96385b31e4bd6b1fd830cccd7.tar.bz2 | |
serial: mxc: enable the RX pipeline
on imx8(mm) the RXDMUXSEL needs to be set for data going over the wire
(as observable on a connected 'scope) to actually make it into the
RXFIFO
the reference manual is not overly clear about this, and only
mentiones that "UCR3_RXDMUXSEL should always be set." - and since the
CR3 register reverts to its reset values after setting the baudrate,
setting this bit is done during '_mxc_serial_setbgr'
Signed-off-by: Johannes Schneider <johannes.schneider@leica-geosystems.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
| -rw-r--r-- | drivers/serial/serial_mxc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 70a0e5e..ee17a96 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -61,6 +61,11 @@ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ + +/* imx8 names these bitsfields instead: */ +#define UCR3_DTRDEN BIT(3) /* bit not used in this chip */ +#define UCR3_RXDMUXSEL BIT(2) /* RXD muxed input selected; 'should always be set' */ + #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ #define UCR3_BPEN (1<<0) /* Preset registers enable */ #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ @@ -176,6 +181,14 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk, writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST, &base->cr2); + + /* + * setting the baudrate triggers a reset, returning cr3 to its + * reset value but UCR3_RXDMUXSEL "should always be set." + * according to the imx8 reference-manual + */ + writel(readl(&base->cr3) | UCR3_RXDMUXSEL, &base->cr3); + writel(UCR1_UARTEN, &base->cr1); } |