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| author | Quentin Schulz <quentin.schulz@theobroma-systems.com> | 2022-11-11 12:25:48 +0100 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2022-12-26 13:36:31 +0800 |
| commit | c08138d7cb4d9f7e079ec3605ca077db6f9b8afa (patch) | |
| tree | 393d8a9fd6cfbab13ff0c98bdbe5f46f64c824fe | |
| parent | edcd87f7e63f8bf4eb3094ee685677a4d6d7903c (diff) | |
| download | u-boot-c08138d7cb4d9f7e079ec3605ca077db6f9b8afa.zip u-boot-c08138d7cb4d9f7e079ec3605ca077db6f9b8afa.tar.gz u-boot-c08138d7cb4d9f7e079ec3605ca077db6f9b8afa.tar.bz2 | |
rockchip: px30: make watchdog and tsadc trigger a first global reset
By default, the PX30 is configured for watchdog and tsadc to trigger a
second global reset which is a more permissive reset than first global
reset.
From TRM part 1 "2.3 System Reset Solution":
glb_srstn_1 will reset the all logic, and
glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs.
This enforces that the watchdog and tsadc trigger glb_srstn_1 as
similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?),
TF-A and Coreboot.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | arch/arm/mach-rockchip/px30/px30.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 0641e6a..ded03ff 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -234,6 +234,7 @@ enum { int arch_cpu_init(void) { static struct px30_grf * const grf = (void *)GRF_BASE; + static struct px30_cru * const cru = (void *)CRU_BASE; u32 __maybe_unused val; #ifdef CONFIG_SPL_BUILD @@ -285,6 +286,9 @@ int arch_cpu_init(void) /* Clear the force_jtag */ rk_clrreg(&grf->cpu_con[1], 1 << 7); + /* Make TSADC and WDT trigger a first global reset */ + clrsetbits_le32(&cru->glb_rst_con, 0x3, 0x3); + return 0; } |