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| author | Quentin Schulz <quentin.schulz@theobroma-systems.com> | 2022-11-14 11:33:46 +0100 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2022-12-26 13:36:31 +0800 |
| commit | 998e90eefce9226a6b8e476a7cec13cb8b81a052 (patch) | |
| tree | 2fcdbb98eaac07bc0426a8241a6c55a3be25f3ca | |
| parent | c08138d7cb4d9f7e079ec3605ca077db6f9b8afa (diff) | |
| download | u-boot-998e90eefce9226a6b8e476a7cec13cb8b81a052.zip u-boot-998e90eefce9226a6b8e476a7cec13cb8b81a052.tar.gz u-boot-998e90eefce9226a6b8e476a7cec13cb8b81a052.tar.bz2 | |
rockchip: clk: add watchdog clock to px30_clk_enable
Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver
can probe since it wants to enable this clock.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_px30.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index 5d46744..33a7348 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1415,6 +1415,9 @@ static int px30_clk_enable(struct clk *clk) case SCLK_GMAC_RMII: /* Required to successfully probe the Designware GMAC driver */ return 0; + case PCLK_WDT_NS: + /* Required to successfully probe the Designware watchdog driver */ + return 0; } debug("%s: unsupported clk %ld\n", __func__, clk->id); |