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| author | Christopher Obbard <chris.obbard@collabora.com> | 2022-11-23 13:59:02 +0000 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2022-12-26 13:36:31 +0800 |
| commit | 6b9adb818bc1afc1475310a8ad37705d2135eed5 (patch) | |
| tree | 6ff47883475c28ed8b2c2f367e8fe3f87965a4e8 | |
| parent | 238112dab8f536069493c2fb6e5b3cd8d18c5d05 (diff) | |
| download | u-boot-6b9adb818bc1afc1475310a8ad37705d2135eed5.zip u-boot-6b9adb818bc1afc1475310a8ad37705d2135eed5.tar.gz u-boot-6b9adb818bc1afc1475310a8ad37705d2135eed5.tar.bz2 | |
configs: roc-pc-rk3399: Enable rockchip efuse support
Enable efuse support which allows reading of the cpuid#, serial#
and also generates a unique mac address from the board's serial.
Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | configs/roc-pc-mezzanine-rk3399_defconfig | 2 | ||||
| -rw-r--r-- | configs/roc-pc-rk3399_defconfig | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 6827c98..e800110 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -22,6 +22,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -50,6 +51,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 6cde762..9327f97 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -23,6 +23,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -51,6 +52,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y |