ram: rockchip: Update ddr pctl regs for px30

Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

2 files changed, 101 insertions, 5 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
index 3a36577..3780dc6 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
@@ -12,7 +12,7 @@
 #endif
 
 struct ddr_pctl_regs {
-	u32 pctl[30][2];
+	u32 pctl[35][2];
 };
 
 /* ddr pctl registers define */
@@ -25,6 +25,7 @@ struct ddr_pctl_regs {
 #define DDR_PCTL2_MRCTRL2		0x1c
 #define DDR_PCTL2_DERATEEN		0x20
 #define DDR_PCTL2_DERATEINT		0x24
+#define DDR_PCTL2_MSTR2			0x28
 #define DDR_PCTL2_PWRCTL		0x30
 #define DDR_PCTL2_PWRTMG		0x34
 #define DDR_PCTL2_HWLPCTL		0x38
@@ -122,8 +123,103 @@ struct ddr_pctl_regs {
 #define DDR_PCTL2_PCFGW_n		0x408
 #define DDR_PCTL2_PCTRL_n		0x490
 
+#define UMCTL2_REGS_FREQ(n)	\
+	((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0)))
+
+/* PCTL2_MSTR */
+#define PCTL2_FREQUENCY_MODE_MASK	(1)
+#define PCTL2_FREQUENCY_MODE_SHIFT	(29)
+#define PCTL2_DLL_OFF_MODE		BIT(15)
+/* PCTL2_STAT */
+#define PCTL2_SELFREF_TYPE_MASK		(3 << 4)
+#define PCTL2_SELFREF_TYPE_SR_NOT_AUTO	(2 << 4)
+#define PCTL2_OPERATING_MODE_MASK	(7)
+#define PCTL2_OPERATING_MODE_INIT	(0)
+#define PCTL2_OPERATING_MODE_NORMAL	(1)
+#define PCTL2_OPERATING_MODE_PD		(2)
+#define PCTL2_OPERATING_MODE_SR		(3)
+/* PCTL2_MRCTRL0 */
+#define PCTL2_MR_WR			BIT(31)
+#define PCTL2_MR_ADDR_SHIFT		(12)
+#define PCTL2_MR_RANK_SHIFT		(4)
+#define PCTL2_MR_TYPE_WR		(0)
+#define PCTL2_MR_TYPE_RD		(1)
+/* PCTL2_MRCTRL1 */
+#define PCTL2_MR_ADDRESS_SHIFT		(8)
+#define PCTL2_MR_DATA_MASK		(0xff)
 /* PCTL2_MRSTAT */
-#define MR_WR_BUSY			BIT(0)
+#define PCTL2_MR_WR_BUSY		BIT(0)
+/* PCTL2_DERATEEN */
+#define PCTL2_DERATE_ENABLE		(1)
+/* PCTL2_PWRCTL */
+#define PCTL2_SELFREF_SW		BIT(5)
+#define PCTL2_POWERDOWN_EN		BIT(1)
+#define PCTL2_SELFREF_EN		(1)
+/* PCTL2_PWRTMG */
+#define PCTL2_SELFREF_TO_X32_MASK	(0xFF)
+#define PCTL2_SELFREF_TO_X32_SHIFT	(16)
+#define PCTL2_POWERDOWN_TO_X32_MASK	(0x1F)
+/* PCTL2_INIT3 */
+#define PCTL2_DDR34_MR0_SHIFT		(16)
+#define PCTL2_LPDDR234_MR1_SHIFT	(16)
+#define PCTL2_DDR34_MR1_SHIFT		(0)
+#define PCTL2_LPDDR234_MR2_SHIFT	(0)
+/* PCTL2_INIT4 */
+#define PCTL2_DDR34_MR2_SHIFT		(16)
+#define PCTL2_LPDDR234_MR3_SHIFT	(16)
+#define PCTL2_DDR34_MR3_SHIFT		(0)
+#define PCTL2_LPDDR4_MR13_SHIFT		(0)
+
+/* PCTL2_INIT6 */
+#define PCTL2_DDR4_MR4_SHIFT		(16)
+#define PCTL2_LPDDR4_MR11_SHIFT		(16)
+#define PCTL2_DDR4_MR5_SHIFT		(0)
+#define PCTL2_LPDDR4_MR12_SHIFT		(0)
+
+/* PCTL2_INIT7 */
+#define PCTL2_LPDDR4_MR22_SHIFT		(16)
+#define PCTL2_DDR4_MR6_SHIFT		(0)
+#define PCTL2_LPDDR4_MR14_SHIFT		(0)
+
+#define PCTL2_MR_MASK			(0xffff)
+
+/* PCTL2_RFSHCTL3 */
+#define PCTL2_DIS_AUTO_REFRESH		(1)
+/* PCTL2_ZQCTL0 */
+#define PCTL2_DIS_AUTO_ZQ		BIT(31)
+#define PCTL2_DIS_SRX_ZQCL		BIT(30)
+/* PCTL2_DFILPCFG0 */
+#define PCTL2_DFI_LP_EN_SR		BIT(8)
+#define PCTL2_DFI_LP_EN_SR_MASK		BIT(8)
+#define PCTL2_DFI_LP_EN_SR_SHIFT	(8)
+/* PCTL2_DFIMISC */
+#define PCTL2_DFI_INIT_COMPLETE_EN	(1)
+/* PCTL2_DFISTAT */
+#define PCTL2_DFI_LP_ACK		BIT(1)
+#define PCTL2_DFI_INIT_COMPLETE		(1)
+/* PCTL2_DBG1 */
+#define PCTL2_DIS_HIF			BIT(1)
+/* PCTL2_DBGCAM */
+#define PCTL2_DBG_WR_Q_EMPTY		BIT(26)
+#define PCTL2_DBG_RD_Q_EMPTY		BIT(25)
+#define PCTL2_DBG_LPR_Q_DEPTH_MASK	(0xffff << 8)
+#define PCTL2_DBG_LPR_Q_DEPTH_EMPTY	(0x0 << 8)
+/* PCTL2_DBGCMD */
+#define PCTL2_RANK1_REFRESH		BIT(1)
+#define PCTL2_RANK0_REFRESH		(1)
+/* PCTL2_DBGSTAT */
+#define PCTL2_RANK1_REFRESH_BUSY	BIT(1)
+#define PCTL2_RANK0_REFRESH_BUSY	(1)
+/* PCTL2_SWCTL */
+#define PCTL2_SW_DONE			(1)
+#define PCTL2_SW_DONE_CLEAR		(0)
+/* PCTL2_SWSTAT */
+#define PCTL2_SW_DONE_ACK		(1)
+/* PCTL2_PSTAT */
+#define PCTL2_WR_PORT_BUSY_0		BIT(16)
+#define PCTL2_RD_PORT_BUSY_0		(1)
+/* PCTL2_PCTRLn */
+#define PCTL2_PORT_EN			(1)
 
 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
diff --git a/drivers/ram/rockchip/sdram_pctl_px30.c b/drivers/ram/rockchip/sdram_pctl_px30.c
index 331d85f..e5c80fb 100644
--- a/drivers/ram/rockchip/sdram_pctl_px30.c
+++ b/drivers/ram/rockchip/sdram_pctl_px30.c
@@ -21,7 +21,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
 	setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
 	while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
 		continue;
-	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
+	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
 		continue;
 }
 
@@ -33,7 +33,7 @@ void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
 		  u32 dramtype)
 {
-	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
+	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
 		continue;
 	if (dramtype == DDR3 || dramtype == DDR4) {
 		writel((mr_num << 12) | (rank << 4) | (0 << 0),
@@ -49,7 +49,7 @@ int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
 	setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
 	while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
 		continue;
-	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
+	while (readl(pctl_base + DDR_PCTL2_MRSTAT) & PCTL2_MR_WR_BUSY)
 		continue;
 
 	return 0;