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| author | Fabio Estevam <festevam@gmail.com> | 2024-03-08 17:13:16 -0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-22 11:10:39 -0400 |
| commit | f0e997dc61a230dbb8f2eacd465d4eb209524d02 (patch) | |
| tree | d8ad48ac1eb71ca2ada63b1eb4f185f470966484 | |
| parent | bcbd1364cb0f32c3879a9c58ab8d61532e0bc4cd (diff) | |
| download | u-boot-f0e997dc61a230dbb8f2eacd465d4eb209524d02.zip u-boot-f0e997dc61a230dbb8f2eacd465d4eb209524d02.tar.gz u-boot-f0e997dc61a230dbb8f2eacd465d4eb209524d02.tar.bz2 | |
clk: clk-imx8qm: Add LPUART IPG entries
Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
the apalis-imx8qm board no longer boots.
The reason is that the imx8qm clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | drivers/clk/imx/clk-imx8qm.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 6c05d07..01e33de 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -95,20 +95,23 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_2; pm_clk = SC_PM_CLK_PER; break; - case IMX8QM_UART0_IPG_CLK: case IMX8QM_UART0_CLK: + case IMX8QM_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART1_CLK: + case IMX8QM_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART2_CLK: + case IMX8QM_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART3_CLK: + case IMX8QM_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -181,18 +184,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART0_CLK: + case IMX8QM_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART1_CLK: + case IMX8QM_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART2_CLK: + case IMX8QM_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART3_CLK: + case IMX8QM_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -283,18 +290,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable) pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART0_CLK: + case IMX8QM_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART1_CLK: + case IMX8QM_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART2_CLK: + case IMX8QM_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART3_CLK: + case IMX8QM_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; |