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| author | Dinesh Maniyam <dinesh.maniyam@intel.com> | 2022-05-31 16:15:17 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-06-17 16:27:05 +0800 |
| commit | 5474fb894cba4de1f8735e02155ca85d81af03de (patch) | |
| tree | 36508879ab50e43aa31bd9edd0d326ef87169e32 | |
| parent | 7f8533078291bc1c96125ec0619ffd5d01ecc83d (diff) | |
| download | u-boot-5474fb894cba4de1f8735e02155ca85d81af03de.zip u-boot-5474fb894cba4de1f8735e02155ca85d81af03de.tar.gz u-boot-5474fb894cba4de1f8735e02155ca85d81af03de.tar.bz2 | |
arm: dts: socfpga: stratix10: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.
Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
| -rwxr-xr-x | arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 61df425..75a2904 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */ #include "socfpga_stratix10-u-boot.dtsi" @@ -10,6 +10,15 @@ /{ aliases { spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; }; |