at91: add support for the PM9263 board of Ronetix GmbH

The PM9263 board is based on the AT91SAM9263-EK board.

Here is the page on Ronetix website:
http://www.ronetix.at/starter_kit_9263.html

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

19 files changed, 1342 insertions, 4 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 03d59b9..6bb03b4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -204,6 +204,10 @@ Klaus Heydeck <heydeck@kieback-peter.de>
 	KUP4K		MPC855
 	KUP4X		MPC859
 
+Ilko Iliev <iliev@ronetix.at>
+
+	PM9263		AT91SAM9263
+
 Gary Jennejohn <garyj@denx.de>
 
 	quad100hd	PPC405EP
diff --git a/MAKEALL b/MAKEALL
index e4eb42b..f13c81a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -582,6 +582,7 @@ LIST_at91="		\
 	kb9202		\
 	mp2usb		\
 	m501sk		\
+	pm9263		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index e91c051..c52894c 100644
--- a/Makefile
+++ b/Makefile
@@ -2749,6 +2749,9 @@ at91sam9rlek_config	:	unconfig
 	fi;
 	@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
 
+pm9263_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
+
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
 integratorap_config	\
@@ -3520,6 +3523,7 @@ clean:
 	       $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
 	       $(obj)board/bf5{18f,26,27,33,38f,48,61}-ez{brd,kit}/u-boot.lds \
 	       $(obj)board/bf5{33,37}-stamp/u-boot.lds			  \
+	       $(obj)cpu/arm926ejs/at91/u-boot.lds			  \
 	       $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile
new file mode 100644
index 0000000..270abd8
--- /dev/null
+++ b/board/ronetix/pm9263/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y += pm9263.o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS-y	:= lowlevel_init.o
+endif
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ronetix/pm9263/config.mk b/board/ronetix/pm9263/config.mk
new file mode 100644
index 0000000..ff2cfd1
--- /dev/null
+++ b/board/ronetix/pm9263/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c
new file mode 100644
index 0000000..fe1a1d2
--- /dev/null
+++ b/board/ronetix/pm9263/led.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
+				      1 << AT91SAM9263_ID_PIOCDE);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/board/ronetix/pm9263/lowlevel_init.S b/board/ronetix/pm9263/lowlevel_init.S
new file mode 100644
index 0000000..c048c91
--- /dev/null
+++ b/board/ronetix/pm9263/lowlevel_init.S
@@ -0,0 +1,279 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91sam9263_matrix.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+.type lowlevel_init,function
+lowlevel_init:
+
+	mov	r5, pc		/* r5 = POS1 + 4 current */
+POS1:
+	ldr	r0, =POS1	/* r0 = POS1 compile */
+	ldr	r2, _TEXT_BASE
+	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
+	sub	r5, r5, r0	/* r0 = TEXT_BASE-1 */
+	sub	r5, r5, #4	/* r1 = text base - current */
+
+	/* memory control configuration 1 */
+	ldr	r0, =SMRDATA
+	ldr	r2, =SMRDATA1
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	sub	r2, r2, r1
+	add	r0, r0, r5
+	add	r2, r2, r5
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 1.
+ * ----------------------------------------------------------------------------
+ * - Check if the PLL is already initialized
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
+	ldr	r0, [r1]
+	and	r0, r0, #3
+	cmp	r0, #0
+	bne	PLL_setup_end
+
+/* ---------------------------------------------------------------------------
+ * - Enable the Main Oscillator
+ * ---------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
+	ldr	r2, =(AT91_BASE_SYS + AT91_PMC_SR)
+	ldr	r0, =0x0000FF01
+	str	r0, [r1]	/* Enable main oscillator, OSCOUNT = 0xFF */
+
+	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
+	mov	r4, #AT91_PMC_MOSCS
+MOSCS_Loop:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_MOSCS
+	bne	MOSCS_Loop
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 2.
+ * ----------------------------------------------------------------------------
+ * Setup PLLA
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
+	ldr	r0, =CONFIG_SYS_PLLAR_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect when the PLLA is locked */
+	mov	r4, #AT91_PMC_LOCKA
+MOSCS_Loop1:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_LOCKA
+	bne	MOSCS_Loop1
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 3.
+ * ----------------------------------------------------------------------------
+ * - Switch on the Main Oscillator 18.432 MHz
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
+
+	/* -Master Clock Controller register PMC_MCKR */
+	ldr	r0, =CONFIG_SYS_MCKR1_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status to detect when the Master clock is ready */
+	mov	r4, #AT91_PMC_MCKRDY
+MCKRDY_Loop:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_MCKRDY
+	bne	MCKRDY_Loop
+
+	ldr	r0, =CONFIG_SYS_MCKR2_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status to detect when the Master clock is ready */
+	mov	r4, #AT91_PMC_MCKRDY
+MCKRDY_Loop1:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_MCKRDY
+	bne	MCKRDY_Loop1
+
+PLL_setup_end:
+
+/* ----------------------------------------------------------------------------
+ * - memory control configuration 2
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
+	ldr	r1, [r0]
+	cmp	r1, #0
+	bne	SDRAM_setup_end
+
+	ldr	r0, =SMRDATA1
+	ldr	r2, =SMRDATA2
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	sub	r2, r2, r1
+	add	r0, r0, r5
+	add	r2, r2, r5
+
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+SDRAM_setup_end:
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word (AT91_BASE_SYS + AT91_WDT_MR)
+	.word CONFIG_SYS_WDTC_WDMR_VAL
+
+	.word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
+	.word CONFIG_SYS_PIOD_PDR_VAL1
+	.word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
+	.word CONFIG_SYS_PIOD_PPUDR_VAL
+	.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
+	.word CONFIG_SYS_PIOD_PPUDR_VAL
+
+	.word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
+	.word CONFIG_SYS_MATRIX_EBI0CSA_VAL
+	.word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
+	.word CONFIG_SYS_MATRIX_EBI1CSA_VAL
+
+	/* flash */
+	.word (AT91_BASE_SYS + AT91_SMC_MODE(0))
+	.word CONFIG_SYS_SMC0_CTRL0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
+	.word CONFIG_SYS_SMC0_CYCLE0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
+	.word CONFIG_SYS_SMC0_PULSE0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
+	.word CONFIG_SYS_SMC0_SETUP0_VAL
+
+	/* PSRAM */
+	.word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
+	.word CONFIG_SYS_SMC1_CTRL0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
+	.word CONFIG_SYS_SMC1_CYCLE0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
+	.word CONFIG_SYS_SMC1_PULSE0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
+	.word CONFIG_SYS_SMC1_SETUP0_VAL
+
+SMRDATA1:
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
+	.word CONFIG_SYS_SDRC_TR_VAL1
+	.word (AT91_BASE_SYS + AT91_SDRAMC_CR)
+	.word CONFIG_SYS_SDRC_CR_VAL
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
+	.word CONFIG_SYS_SDRC_MDR_VAL
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL1
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL2
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL3
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL4
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL5
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL6
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL7
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL8
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL9
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL4
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL10
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL5
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL11
+	.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
+	.word CONFIG_SYS_SDRC_TR_VAL2
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL12
+	/* User reset enable*/
+	.word (AT91_BASE_SYS + AT91_RSTC_MR)
+	.word CONFIG_SYS_RSTC_RMR_VAL
+#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
+	/* MATRIX_MCFG - REMAP all masters */
+	.word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
+	.word 0x1FF
+#endif
+
+SMRDATA2:
+	.word 0
diff --git a/board/ronetix/pm9263/partition.c b/board/ronetix/pm9263/partition.c
new file mode 100644
index 0000000..95ac398
--- /dev/null
+++ b/board/ronetix/pm9263/partition.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+#ifdef CONFIG_SYS_USE_DATAFLASH
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR,   0, ""},
+};
+
+#endif
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
new file mode 100644
index 0000000..d24ef9a
--- /dev/null
+++ b/board/ronetix/pm9263/pm9263.c
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9263_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <dataflash.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9263_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+	at91_sys_write(AT91_MATRIX_EBI0CSA,
+		       csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(2));
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9263_macb_hw_init(void)
+{
+	/*
+	 * PB27 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_gpio_output(AT91_PIN_PB27, 1);
+	at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PC25) => PHY normal mode (not Test mode)
+	 *	ERX0 (PE25) => PHY ADDR0
+	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PC25),
+	       pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
+	writel(pin_to_mask(AT91_PIN_PE25) |
+	       pin_to_mask(AT91_PIN_PE26),
+	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
+
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PC25),
+	       pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
+	writel(pin_to_mask(AT91_PIN_PE25) |
+	       pin_to_mask(AT91_PIN_PE26),
+	       pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
+}
+
+#ifdef CONFIG_LCD_IN_PSRAM
+
+#define PSRAM_CRE_PIN	AT91_PIN_PB29
+#define PSRAM_CTRL_REG	(PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
+
+/* Initialize the PSRAM memory */
+static int pm9263_lcd_hw_psram_init(void)
+{
+	volatile uint16_t x;
+
+	/* setup PB29 as output */
+	at91_set_gpio_output(PSRAM_CRE_PIN, 1);
+
+	at91_set_gpio_value(PSRAM_CRE_PIN, 0);	/* set PSRAM_CRE_PIN to '0' */
+
+	/* PSRAM: write BCR */
+	x = readw(PSRAM_CTRL_REG);
+	x = readw(PSRAM_CTRL_REG);
+	writew(1, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+	writew(0x9d4f, PSRAM_CTRL_REG);	/* write the BCR */
+
+	/* write RCR of the PSRAM */
+	x = readw(PSRAM_CTRL_REG);
+	x = readw(PSRAM_CTRL_REG);
+	writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+	/* set RCR; 0x10-async mode,0x90-page mode */
+	writew(0x90, PSRAM_CTRL_REG);
+
+	/*
+	 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
+	 * MT45W2M16B - CRE must be 0
+	 * MT45W2M16A - CRE must be 1
+	 */
+	writew(0x1234, PHYS_PSRAM);
+	writew(0x5678, PHYS_PSRAM + 2);
+
+	/* test if the chip is MT45W2M16B */
+	if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
+		/* try with CRE=1 (MT45W2M16A) */
+		at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
+
+		/* write RCR of the PSRAM */
+		x = readw(PSRAM_CTRL_REG);
+		x = readw(PSRAM_CTRL_REG);
+		writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
+		/* set RCR;0x10-async mode,0x90-page mode */
+		writew(0x90, PSRAM_CTRL_REG);
+
+
+		writew(0x1234, PHYS_PSRAM);
+		writew(0x5678, PHYS_PSRAM+2);
+		if ((readw(PHYS_PSRAM) != 0x1234)
+		   || (readw(PHYS_PSRAM + 2) != 0x5678))
+			return 1;
+
+	}
+
+	/* Bus matrix */
+	at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR );
+	at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
+				(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
+				AT91_MATRIX_DEFMSTR_TYPE_FIXED |
+				(AT91_MATRIX_SLOT_CYCLE & (0x80 << 0)));
+
+	return 0;
+}
+#endif
+
+static void pm9263_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC0, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
+	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+
+	/* Power Control */
+	at91_set_gpio_output(AT91_PIN_PA22, 1);
+	at91_set_gpio_value(AT91_PIN_PA22, 0);	/* power down */
+
+#ifdef CONFIG_LCD_IN_PSRAM
+	/* initialize te PSRAM */
+	int stat = pm9263_lcd_hw_psram_init();
+
+	gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE;
+#else
+	gd->fb_base = AT91SAM9263_SRAM0_BASE;
+#endif
+
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+extern flash_info_t flash_info[];
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size, flash_size, dataflash_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2009 Ronetix GmbH\n");
+	lcd_printf ("support@ronetix.at\n");
+	lcd_printf ("%s CPU at %s MHz",
+		AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+
+	dataflash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+				dataflash_info[i].Device.pages_size;
+
+	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
+			"4 MB PSRAM, %ld MB DataFlash\n",
+		dram_size >> 20,
+		nand_size >> 20,
+		flash_size >> 20,
+		dataflash_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	at91_sys_write(AT91_PMC_PCER,
+					(1 << AT91SAM9263_ID_PIOA) |
+					(1 << AT91SAM9263_ID_PIOCDE) |
+					(1 << AT91SAM9263_ID_PIOB));
+
+	/* arch number of AT91SAM9263EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	pm9263_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	pm9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	pm9263_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+	char *ss;
+	char buf[32];
+
+	printf ("Board : Ronetix PM9263\n");
+	printf ("Crystal frequency: %8s MHz\n",
+					strmhz(buf, get_main_clk_rate()));
+	printf ("CPU clock        : %8s MHz\n",
+					strmhz(buf, get_cpu_clk_rate()));
+	printf ("Master clock     : %8s MHz\n",
+					strmhz(buf, get_mck_clk_rate()));
+
+	switch (gd->fb_base) {
+	case PHYS_PSRAM:
+		ss = "(PSRAM)";
+		break;
+
+	case AT91SAM9263_SRAM0_BASE:
+		ss = "(Internal SRAM)";
+		break;
+
+	default:
+		ss = "";
+		break;
+	}
+	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
+
+	printf ("\n");
+	return 0;
+}
+#endif
diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile
index 3d45c42..fbc82d1 100644
--- a/cpu/arm926ejs/at91/Makefile
+++ b/cpu/arm926ejs/at91/Makefile
@@ -63,11 +63,14 @@ SOBJS	= lowlevel_init.o
 SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
 
-all:	$(obj).depend $(LIB)
+all:	$(obj).depend $(LIB) $(obj)u-boot.lds
 
 $(LIB):	$(OBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
 
+$(obj)u-boot.lds: u-boot.lds.S
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -DCONFIG_BOARDDIR=$(BOARDDIR) -P $^ > $@
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/cpu/arm926ejs/at91/config.mk b/cpu/arm926ejs/at91/config.mk
index 06177e6..147bd4c 100644
--- a/cpu/arm926ejs/at91/config.mk
+++ b/cpu/arm926ejs/at91/config.mk
@@ -1,2 +1,2 @@
 PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
-LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91/u-boot.lds
+LDSCRIPT := $(OBJTREE)/cpu/arm926ejs/at91/u-boot.lds
diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S
index ec6ad5d..54b3f3d 100644
--- a/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/cpu/arm926ejs/at91/lowlevel_init.S
@@ -30,6 +30,8 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 
 .globl lowlevel_init
+.weak lowlevel_init
+.set lowlevel_init,function
 lowlevel_init:
 
 	/*
diff --git a/cpu/arm926ejs/at91/u-boot.lds b/cpu/arm926ejs/at91/u-boot.lds.S
index ebb1f93..4e82bca 100644
--- a/cpu/arm926ejs/at91/u-boot.lds
+++ b/cpu/arm926ejs/at91/u-boot.lds.S
@@ -21,6 +21,8 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
+
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 /*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
 OUTPUT_ARCH(arm)
@@ -32,8 +34,11 @@ SECTIONS
 	. = ALIGN(4);
 	.text :
 	{
-	  cpu/arm926ejs/start.o	(.text)
-	  *(.text)
+		cpu/arm926ejs/start.o	(.text)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+		board/CONFIG_BOARDDIR/lowlevel_init.o (.text)
+#endif
+		*(.text)
 	}
 
 	. = ALIGN(4);
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index 98251cb..07b265f 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -106,6 +106,7 @@
 #define AT91_USART2	AT91SAM9263_BASE_US2
 
 #define AT91_SMC	AT91_SMC0
+#define AT91_SDRAMC	AT91_SDRAMC0
 
 /*
  * Internal Memory.
diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
new file mode 100644
index 0000000..5af2b54
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
@@ -0,0 +1,87 @@
+/*
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR		(AT91_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
+#define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
+#define			AT91_SDRAMC_MODE_NORMAL		0
+#define			AT91_SDRAMC_MODE_NOP		1
+#define			AT91_SDRAMC_MODE_PRECHARGE	2
+#define			AT91_SDRAMC_MODE_LMR		3
+#define			AT91_SDRAMC_MODE_REFRESH	4
+#define			AT91_SDRAMC_MODE_EXT_LMR	5
+#define			AT91_SDRAMC_MODE_DEEP		6
+
+#define AT91_SDRAMC_TR		(AT91_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
+#define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR		(AT91_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
+#define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
+#define			AT91_SDRAMC_NC_8	(0 << 0)
+#define			AT91_SDRAMC_NC_9	(1 << 0)
+#define			AT91_SDRAMC_NC_10	(2 << 0)
+#define			AT91_SDRAMC_NC_11	(3 << 0)
+#define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
+#define			AT91_SDRAMC_NR_11	(0 << 2)
+#define			AT91_SDRAMC_NR_12	(1 << 2)
+#define			AT91_SDRAMC_NR_13	(2 << 2)
+#define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
+#define			AT91_SDRAMC_NB_2	(0 << 4)
+#define			AT91_SDRAMC_NB_4	(1 << 4)
+#define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
+#define			AT91_SDRAMC_CAS_1	(1 << 5)
+#define			AT91_SDRAMC_CAS_2	(2 << 5)
+#define			AT91_SDRAMC_CAS_3	(3 << 5)
+#define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
+#define			AT91_SDRAMC_DBW_32	(0 << 7)
+#define			AT91_SDRAMC_DBW_16	(1 << 7)
+#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
+#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
+#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
+#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
+#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
+#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR		(AT91_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
+#define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
+#define			AT91_SDRAMC_LPCB_DISABLE		0
+#define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
+#define			AT91_SDRAMC_LPCB_POWER_DOWN		2
+#define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
+#define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
+#define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
+#define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
+#define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
+#define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
+#define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
+#define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
+
+#define AT91_SDRAMC_IER		(AT91_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR		(AT91_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR		(AT91_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR		(AT91_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
+#define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR		(AT91_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
+#define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
+#define			AT91_SDRAMC_MD_SDRAM		0
+#define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
+
+
+#endif
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 6b46a36..8704106 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -48,6 +48,23 @@
 #error "Unsupported AT91 processor"
 #endif
 
+/* External Memory Map */
+#define AT91_CHIPSELECT_0	0x10000000
+#define AT91_CHIPSELECT_1	0x20000000
+#define AT91_CHIPSELECT_2	0x30000000
+#define AT91_CHIPSELECT_3	0x40000000
+#define AT91_CHIPSELECT_4	0x50000000
+#define AT91_CHIPSELECT_5	0x60000000
+#define AT91_CHIPSELECT_6	0x70000000
+#define AT91_CHIPSELECT_7	0x80000000
+
+/* SDRAM */
+#ifdef CONFIG_DRAM_BASE
+#define AT91_SDRAM_BASE		CONFIG_DRAM_BASE
+#else
+#define AT91_SDRAM_BASE		AT91_CHIPSELECT_1
+#endif
+
 /* Clocks */
 #define AT91_SLOW_CLOCK		32768		/* slow clock */
 
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
new file mode 100644
index 0000000..9ae737f
--- /dev/null
+++ b/include/configs/pm9263.h
@@ -0,0 +1,367 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * Configuation settings for the RONETIX PM9263 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME		"AT91SAM9263"
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MASTER_PLL_DIV		15
+#define MASTER_PLL_MUL		162
+#define MAIN_PLL_DIV		2	/* 2 or 4 */
+#define AT91_MAIN_CLOCK	18432000
+
+#define CONFIG_SYS_HZ		1000000
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#define CONFIG_AT91SAM9263	1	/* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_PM9263		1	/* on a Ronetix PM9263 Board	*/
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL	0x00002001	/* CKGR_MOR - enable main osc. */
+#define CONFIG_SYS_PLLAR_VAL	\
+		(0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+#if (MAIN_PLL_DIV == 2)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL		0x00000100
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL		0x00000102
+#else
+/* PCK/4 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL		0x00000200
+/* PCK/4 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL		0x00000202
+#endif
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL	0x0001010A
+/* EBI1_CSA, 3.3v, no pull-ups */
+#define CONFIG_SYS_MATRIX_EBI1CSA_VAL	0x00010100
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+#define CONFIG_SYS_SDRC_CR_VAL		0x85227279	/*CL3*/
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		0
+#define CONFIG_SYS_SDRC_MR_VAL2		0x00000002	/* SDRAMC_MR */
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		4		/* SDRC_MR */
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		3		/* SDRC_MR */
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		0		/* SDRC_MR */
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL	0x0A0A0A0A	/* SMC_SETUP */
+#define CONFIG_SYS_SMC0_PULSE0_VAL	0x0B0B0B0B	/* SMC_PULSE */
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	0x00160016	/* SMC_CYCLE */
+#define CONFIG_SYS_SMC0_CTRL0_VAL	0x00161003	/* SMC_MODE */
+
+/* setup SMC1, CS0 (PSRAM) - 16-bit */
+#define CONFIG_SYS_SMC1_SETUP0_VAL	0x00000000	/* SMC_SETUP */
+#define CONFIG_SYS_SMC1_PULSE0_VAL	0x07020707	/* SMC_PULSE */
+#define CONFIG_SYS_SMC1_CYCLE0_VAL	0x00080008	/* SMC_CYCLE */
+#define CONFIG_SYS_SMC1_CTRL0_VAL	0x31001000	/* SMC_MODE */
+
+#define CONFIG_SYS_RSTC_RMR_VAL		0xA5000301	/* user reset enable */
+
+/* Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL	0x3fff8fff	/* disable watchdog */
+
+/* */
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_USER_LOWLEVEL_INIT	1
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART	1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_SYS_WHITE_ON_BLACK	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+#define CONFIG_LCD_IN_PSRAM		1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define	CONFIG_RED_LED		AT91_PIN_PB7	/* this is the power led */
+#define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* this is the user1 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x20000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH			1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK				15000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* NOR flash, if populated */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define PHYS_FLASH_1			0x10000000
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PB30
+#endif
+
+#define CONFIG_CMD_JFFS2		1
+#define CONFIG_JFFS2_CMDLINE		1
+#define CONFIG_JFFS2_NAND		1
+#define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/
+
+/* PSRAM */
+#define	PHYS_PSRAM			0x70000000
+#define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_MULTI		1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_DOS_PARTITION			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE			1
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#define CONFIG_SYS_USE_FLASH	1
+#undef CONFIG_SYS_USE_DATAFLASH
+#undef CONFIG_SYS_USE_NANDFLASH
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				"mtdparts=at91_nand:-(root) "\
+				"rw rootfstype=jffs2"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "		\
+				"root=/dev/mtdblock5 "		\
+				"mtdparts=at91_nand:"		\
+					"128k(bootstrap)ro,"	\
+					"256k(uboot)ro,"	\
+					"128k(env1)ro,"		\
+					"128k(env2)ro,"		\
+					"2M(linux),"		\
+					"-(root) "		\
+				"rw rootfstype=jffs2"
+
+#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define	CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
+
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+#define CONFIG_ROOTPATH			/ronetix/rootfs
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"
+
+#define CONFIG_CON_ROT			"fbcon=rotate:3 "
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock4 rootfstype=jffs2 "\
+					CONFIG_CON_ROT
+
+#define MTDIDS_DEFAULT			"nor0=physmap-flash.0,nand0=nand"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=physmap-flash.0:"	\
+		"256k(u-boot)ro,"	\
+		"64k(u-boot-env)ro,"	\
+		"1408k(kernel),"	\
+		"-(rootfs);"		\
+	"nand:-(nand)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"mtdids=" MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"partition=nand0,0\0"					\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+		CONFIG_CON_ROT					\
+		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
+	"addip=setenv bootargs $(bootargs) "			\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
+		":$(hostname):eth0:off\0"			\
+	"ramboot=tftpboot 0x22000000 vmImage;"			\
+		"run ramargs;run addip;bootm 22000000\0"	\
+	"nfsboot=tftpboot 0x22000000 vmImage;"			\
+		"run nfsargs;run addip;bootm 22000000\0"	\
+	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
+	""
+
+#else
+#error "Undefined memory device"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT		"u-boot-pm9263> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+
+#define ROUND(A, B)			(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/tools/Makefile b/tools/Makefile
index 70d87b0..43c284c 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -122,6 +122,9 @@ endif
 ifeq ($(VENDOR),atmel)
 LOGO_BMP= logos/atmel.bmp
 endif
+ifeq ($(VENDOR),ronetix)
+LOGO_BMP= logos/ronetix.bmp
+endif
 
 # now $(obj) is defined
 SRCS	+= $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
diff --git a/tools/logos/ronetix.bmp b/tools/logos/ronetix.bmp
new file mode 100644
index 0000000..f956813
--- /dev/null
+++ b/tools/logos/ronetix.bmp