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| author | Pali Rohár <pali@kernel.org> | 2021-09-24 22:59:14 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-10-08 08:33:52 +0200 |
| commit | cfd4a8ad0f205be4270c382a1a2ce2701b2ddde7 (patch) | |
| tree | 1b240f16bd108843d0176cef327977449f1a70be | |
| parent | 021a98a2d6512bf59581675a997d659b18c09306 (diff) | |
| download | u-boot-cfd4a8ad0f205be4270c382a1a2ce2701b2ddde7.zip u-boot-cfd4a8ad0f205be4270c382a1a2ce2701b2ddde7.tar.gz u-boot-cfd4a8ad0f205be4270c382a1a2ce2701b2ddde7.tar.bz2 | |
arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code
Replace magic register offsets by macros to make code more readable.
Add comments about what this code is doing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 37 |
1 files changed, 25 insertions, 12 deletions
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index bb7d24b..7b47105 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -1721,31 +1721,44 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, reg_data &= ~0x4000; reg_write(SOC_CONTROL_REG1, reg_data); - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x6c)); + /* Set Maximum Link Width to X1 or X4 */ + reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG)); reg_data &= ~0x3f0; if (is_pex_by1 == 1) reg_data |= 0x10; else reg_data |= 0x40; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), + reg_write(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG), reg_data); - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x6c)); + /* Set Maximum Link Speed to 5 GT/s */ + reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG)); reg_data &= ~0xf; reg_data |= 0x2; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), + reg_write(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG), reg_data); - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x70)); + /* + * Set Common Clock Configuration to indicates + * that both devices on the link use a + * distributed common reference clock. + */ + reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CTRL_STAT_REG)); reg_data &= ~0x40; reg_data |= 0x40; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70), + reg_write(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CTRL_STAT_REG), reg_data); } |