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| author | Mike Frysinger <vapier@gentoo.org> | 2008-10-12 23:49:13 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-03-24 20:36:29 -0400 |
| commit | 9f64ba2412d3cede9eb1f290987e5c3a28df3232 (patch) | |
| tree | 16e19e60b4865b7cb36f11e2873e0f418edf7edf | |
| parent | 23fd959eeaaa0434ac7f9c1191de66c76d97d699 (diff) | |
| download | u-boot-9f64ba2412d3cede9eb1f290987e5c3a28df3232.zip u-boot-9f64ba2412d3cede9eb1f290987e5c3a28df3232.tar.gz u-boot-9f64ba2412d3cede9eb1f290987e5c3a28df3232.tar.bz2 | |
Blackfin: bf533-stamp: bump up default clocks
Since the hardware can handle it, bump the default clocks from 80mhz SCLK
and 398mhz CCLK to 100mhz SCLK and 498mhz CCLK.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| -rw-r--r-- | include/configs/bf533-stamp.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index c6fd038..d8e1ffc 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -30,7 +30,7 @@ #define CONFIG_PLL_BYPASS 0 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ /* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 36 +#define CONFIG_VCO_MULT 45 /* CCLK_DIV controls the core clock divider */ /* Values can be 1, 2, 4, or 8 ONLY */ #define CONFIG_CCLK_DIV 1 |