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| author | Zong Li <zong.li@sifive.com> | 2021-06-30 23:23:50 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-07-06 20:24:26 +0800 |
| commit | 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829 (patch) | |
| tree | 62d2ac2c805629f26ab5f0709d7d4775020587ea | |
| parent | ffe9a394df0cf4ec14331ce425938409289e5780 (diff) | |
| download | u-boot-4b4159d0f31ca3e0174ccfdce9a24a1fe3671829.zip u-boot-4b4159d0f31ca3e0174ccfdce9a24a1fe3671829.tar.gz u-boot-4b4159d0f31ca3e0174ccfdce9a24a1fe3671829.tar.bz2 | |
board: sifive: support spl multi-dtb on unmatched board
There are two revisions of unmatched board with different DDR timing,
we'd like to support multi-dtb mechanism in SPL, then it selects the
right DTB at runtime according to PCB revision in I2C EEPROM.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | board/sifive/unmatched/spl.c | 28 | ||||
| -rw-r--r-- | configs/sifive_unmatched_defconfig | 4 |
2 files changed, 30 insertions, 2 deletions
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c index 5e1333b..74134b0 100644 --- a/board/sifive/unmatched/spl.c +++ b/board/sifive/unmatched/spl.c @@ -10,11 +10,14 @@ #include <spl.h> #include <misc.h> #include <log.h> +#include <fdtdec.h> +#include <dm/root.h> #include <linux/delay.h> #include <linux/io.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/spl.h> +#include <asm/arch/eeprom.h> #define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12) @@ -26,6 +29,16 @@ int spl_board_init_f(void) { int ret; +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) + int rescan; + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } +#endif + ret = spl_soc_init(); if (ret) { debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret); @@ -79,7 +92,18 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { - /* boot using first FIT config */ - return 0; + /* + * Apply different DDR params on different board revision. + * Use PCB revision which is byte 0x7 in I2C platform EEPROM + * to distinguish that. + */ + if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3 && + !strcmp(name, "hifive-unmatched-a00")) + return 0; + else if (get_pcb_revision_from_eeprom() != PCB_REVISION_REV3 && + !strcmp(name, "hifive-unmatched-a00-rev1")) + return 0; + + return -1; } #endif diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 44edfd2..3a45670 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -41,3 +41,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SPL_OF_LIST="hifive-unmatched-a00 hifive-unmatched-a00-rev1" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 |