driver:i2c:s3c24x0: adapt driver to new i2c

This patch adapts the s3c24x0 driver to the new i2c framework.
Config file is modified for all the boards that use the driver.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
CC: Heiko Schocher <hs@denx.de>
CC: Inderpal Singh <inderpal.singh@linaro.org>
CC: David Müller <d.mueller@elsoft.ch>
CC: Chander Kashyap <k.chander@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>

10 files changed, 170 insertions, 121 deletions

diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
index 6bcc883..6aa0509 100644
--- a/board/samsung/smdk5250/exynos5-dt.c
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -150,8 +150,6 @@ int power_init_board(void)
 
 	set_ps_hold_ctrl();
 
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
 	if (pmic_init(I2C_PMIC))
 		return -1;
 
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 7012c13..44be5fc 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -57,15 +57,18 @@ int board_init(void)
 
 void i2c_init_board(void)
 {
-	struct exynos4_gpio_part1 *gpio1 =
-		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+	int err;
 	struct exynos4_gpio_part2 *gpio2 =
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 
-	/* I2C_5 -> PMIC -> Adapter 0 */
-	s5p_gpio_direction_output(&gpio1->b, 7, 1);
-	s5p_gpio_direction_output(&gpio1->b, 6, 1);
-	/* I2C_9 -> FG -> Adapter 1 */
+	/* I2C_5 -> PMIC */
+	err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("I2C%d not configured\n", (I2C_5));
+		return;
+	}
+
+	/* I2C_8 -> FG */
 	s5p_gpio_direction_output(&gpio2->y4, 0, 1);
 	s5p_gpio_direction_output(&gpio2->y4, 1, 1);
 }
@@ -290,10 +293,10 @@ int power_init_board(void)
 	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 	 * to logical I2C adapter 1
 	 */
-	ret = pmic_init(I2C_0);
+	ret = pmic_init(I2C_5);
 	ret |= pmic_init_max8997();
-	ret |= power_fg_init(I2C_1);
-	ret |= power_muic_init(I2C_0);
+	ret |= power_fg_init(I2C_8);
+	ret |= power_muic_init(I2C_5);
 	ret |= power_bat_init(0);
 	if (ret)
 		return ret;
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index d44d825..8df85ee 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -115,12 +115,17 @@ static void board_external_gpio_init(void)
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 static void board_init_i2c(void)
 {
+	int err;
+
 	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
 	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
 
 	/* I2C_7 */
-	s5p_gpio_direction_output(&gpio1->d0, 2, 1);
-	s5p_gpio_direction_output(&gpio1->d0, 3, 1);
+	err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
+	if (err) {
+		debug("I2C%d not configured\n", (I2C_7));
+		return;
+	}
 
 	/* I2C_8 */
 	s5p_gpio_direction_output(&gpio1->f1, 4, 1);
@@ -132,6 +137,24 @@ static void board_init_i2c(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_I2C_SOFT
+int get_soft_i2c_scl_pin(void)
+{
+	if (I2C_ADAP_HWNR)
+		return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */
+	else
+		return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */
+}
+
+int get_soft_i2c_sda_pin(void)
+{
+	if (I2C_ADAP_HWNR)
+		return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */
+	else
+		return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */
+}
+#endif
+
 int board_early_init_f(void)
 {
 	check_hw_revision();
@@ -167,11 +190,11 @@ int power_init_board(void)
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 	board_init_i2c();
 #endif
-	pmic_init(I2C_0);		/* I2C adapter 0 - bus name I2C_5 */
+	pmic_init(I2C_7);		/* I2C adapter 7 - bus name s3c24x0_7 */
 	pmic_init_max77686();
-	pmic_init_max77693(I2C_2);	/* I2C adapter 2 - bus name I2C_10 */
-	power_muic_init(I2C_2);		/* I2C adapter 2 - bus name I2C_10 */
-	power_fg_init(I2C_1);		/* I2C adapter 1 - bus name I2C_9 */
+	pmic_init_max77693(I2C_9);	/* I2C adapter 9 - bus name soft1 */
+	power_muic_init(I2C_9);		/* I2C adapter 9 - bus name soft1 */
+	power_fg_init(I2C_8);		/* I2C adapter 8 - bus name soft0 */
 	power_bat_init(0);
 
 	p_chrg = pmic_get("MAX77693_PMIC");
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 553b519..fa3a875 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
 obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
-obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
@@ -24,6 +23,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
 obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
 obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index f77a9d1..5dc35e7 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -23,8 +23,6 @@
 #include <i2c.h>
 #include "s3c24x0_i2c.h"
 
-#ifdef CONFIG_HARD_I2C
-
 #define	I2C_WRITE	0
 #define I2C_READ	1
 
@@ -127,7 +125,6 @@
  * For SPL boot some boards need i2c before SDRAM is initialised so force
  * variables to live in SRAM
  */
-static unsigned int g_current_bus __attribute__((section(".data")));
 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
 			__attribute__((section(".data")));
 
@@ -254,17 +251,17 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 	writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 }
 
-static struct s3c24x0_i2c *get_base_i2c(void)
+static struct s3c24x0_i2c *get_base_i2c(int bus)
 {
 #ifdef CONFIG_EXYNOS4
 	struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 							+ (EXYNOS4_I2C_SPACING
-							* g_current_bus));
+							* bus));
 	return i2c;
 #elif defined CONFIG_EXYNOS5
 	struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 							+ (EXYNOS5_I2C_SPACING
-							* g_current_bus));
+							* bus));
 	return i2c;
 #else
 	return s3c24x0_get_base_i2c();
@@ -298,7 +295,6 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 }
 
-#ifdef CONFIG_I2C_MULTI_BUS
 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 {
 	struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
@@ -330,7 +326,6 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 	}
 	return -1;
 }
-#endif
 
 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
 {
@@ -401,49 +396,18 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
 	hsi2c_ch_init(i2c_bus);
 }
 
-/*
- * MULTI BUS I2C support
- */
-
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
-{
-	struct s3c24x0_i2c_bus *i2c_bus;
-
-	i2c_bus = get_bus(bus);
-	if (!i2c_bus)
-		return -1;
-	g_current_bus = bus;
-
-	if (i2c_bus->is_highspeed) {
-		if (hsi2c_get_clk_details(i2c_bus))
-			return -1;
-		hsi2c_ch_init(i2c_bus);
-	} else {
-		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
-						CONFIG_SYS_I2C_SLAVE);
-	}
-
-	return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
-	return g_current_bus;
-}
-#endif
-
-void i2c_init(int speed, int slaveadd)
+static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	struct s3c24x0_i2c *i2c;
+	struct s3c24x0_i2c_bus *bus;
+
 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 #endif
 	ulong start_time = get_timer(0);
 
 	/* By default i2c channel 0 is the current bus */
-	g_current_bus = 0;
-	i2c = get_base_i2c();
+	i2c = get_base_i2c(adap->hwadapnr);
 
 	/*
 	 * In case the previous transfer is still going, wait to give it a
@@ -505,6 +469,10 @@ void i2c_init(int speed, int slaveadd)
 	}
 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
 	i2c_ch_init(i2c, speed, slaveadd);
+
+	bus = &i2c_bus[adap->hwadapnr];
+	bus->active = true;
+	bus->regs = i2c;
 }
 
 /*
@@ -728,6 +696,29 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
 	return rv;
 }
 
+static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
+					  unsigned int speed)
+{
+	struct s3c24x0_i2c_bus *i2c_bus;
+
+	i2c_bus = get_bus(adap->hwadapnr);
+	if (!i2c_bus)
+		return -1;
+
+	i2c_bus->clock_frequency = speed;
+
+	if (i2c_bus->is_highspeed) {
+		if (hsi2c_get_clk_details(i2c_bus))
+			return -1;
+		hsi2c_ch_init(i2c_bus);
+	} else {
+		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
+			    CONFIG_SYS_I2C_S3C24X0_SLAVE);
+	}
+
+	return 0;
+}
+
 /*
  * cmd_type is 0 for write, 1 for read.
  *
@@ -840,13 +831,13 @@ bailout:
 	return result;
 }
 
-int i2c_probe(uchar chip)
+static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar buf[1];
 	int ret;
 
-	i2c_bus = get_bus(g_current_bus);
+	i2c_bus = get_bus(adap->hwadapnr);
 	if (!i2c_bus)
 		return -1;
 	buf[0] = 0;
@@ -864,11 +855,11 @@ int i2c_probe(uchar chip)
 				I2C_READ, chip << 1, 0, 0, buf, 1);
 	}
 
-
 	return ret != I2C_OK;
 }
 
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			    int alen, uchar *buffer, int len)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar xaddr[4];
@@ -902,7 +893,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		chip |= ((addr >> (alen * 8)) &
 			 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-	i2c_bus = get_bus(g_current_bus);
+	i2c_bus = get_bus(adap->hwadapnr);
 	if (!i2c_bus)
 		return -1;
 
@@ -922,7 +913,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 	return 0;
 }
 
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			 int alen, uchar *buffer, int len)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
 	uchar xaddr[4];
@@ -955,7 +947,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		chip |= ((addr >> (alen * 8)) &
 			 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-	i2c_bus = get_bus(g_current_bus);
+	i2c_bus = get_bus(adap->hwadapnr);
 	if (!i2c_bus)
 		return -1;
 
@@ -1001,8 +993,8 @@ static void process_nodes(const void *blob, int node_list[], int count,
 
 		bus->id = pinmux_decode_periph_id(blob, node);
 		bus->clock_frequency = fdtdec_get_int(blob, node,
-						      "clock-frequency",
-						      CONFIG_SYS_I2C_SPEED);
+						"clock-frequency",
+						CONFIG_SYS_I2C_S3C24X0_SPEED);
 		bus->node = node;
 		bus->bus_num = i;
 		exynos_pinmux_config(bus->id, 0);
@@ -1044,7 +1036,6 @@ int i2c_get_bus_num_fdt(int node)
 	return -1;
 }
 
-#ifdef CONFIG_I2C_MULTI_BUS
 int i2c_reset_port_fdt(const void *blob, int node)
 {
 	struct s3c24x0_i2c_bus *i2c_bus;
@@ -1068,12 +1059,61 @@ int i2c_reset_port_fdt(const void *blob, int node)
 		hsi2c_ch_init(i2c_bus);
 	} else {
 		i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
-						CONFIG_SYS_I2C_SLAVE);
+			    CONFIG_SYS_I2C_S3C24X0_SLAVE);
 	}
 
 	return 0;
 }
 #endif
-#endif
 
-#endif /* CONFIG_HARD_I2C */
+/*
+ * Register s3c24x0 i2c adapters
+ */
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 0)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 1)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 2)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 3)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 4)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 5)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 6)
+U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+			 s3c24x0_i2c_read, s3c24x0_i2c_write,
+			 s3c24x0_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_S3C24X0_SPEED,
+			 CONFIG_SYS_I2C_S3C24X0_SLAVE,
+			 7)
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 79a6079..57b620d 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -73,12 +73,12 @@
  * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
  * address 0x50 with 16bit addressing
  */
-#define CONFIG_HARD_I2C				/* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave addr */
+#define CONFIG_SYS_I2C
 
 /* we use the built-in I2C controller */
-#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED    100000	/* I2C speed */
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x7F	/* I2C slave addr */
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 45fa047..ea8753b 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -214,13 +214,12 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_MAX_I2C_NUM	8
-#define CONFIG_SYS_I2C_SLAVE    0x0
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
 #define CONFIG_I2C_EDID
 
 /* PMIC */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index bdefee1..0155322 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -249,13 +249,13 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_MAX_I2C_NUM	8
-#define CONFIG_SYS_I2C_SLAVE    0x0
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
 #define CONFIG_I2C_EDID
 
 /* PMIC */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 3d080c4..f163303 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -16,6 +16,7 @@
  */
 #define CONFIG_SAMSUNG		/* in a SAMSUNG core */
 #define CONFIG_S5P		/* which is in a S5P Family */
+#define CONFIG_EXYNOS4		/* which is in a EXYNOS4XXX */
 #define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
 #define CONFIG_TRATS		/* working with TRATS */
 #define CONFIG_TIZEN		/* TIZEN lib */
@@ -268,31 +269,21 @@
 #define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0xFE
+#define CONFIG_MAX_I2C_NUM		8
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x7F
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS	15
 
 #include <asm/arch/gpio.h>
 
-/* I2C PMIC */
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
-
 /* I2C FG */
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
-
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0)
 
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 0e93836..3bcdfb1 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -260,30 +260,25 @@
 #include <asm/arch/gpio.h>
 
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0
+#define CONFIG_MAX_I2C_NUM		8
+#define CONFIG_SYS_I2C_SOFT
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
 #define I2C_SOFT_DECLARATIONS2
 #define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x00
-#define I2C_SOFT_DECLARATIONS3
-#define CONFIG_SYS_I2C_SOFT_SPEED_3     50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_3     0x00
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 #define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SOFT_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS		15
-
-#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
-#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
-#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
-#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
-#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
-#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
-#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
-#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
-#define I2C_INIT multi_i2c_init()
+
+#ifndef __ASSEMBLY__
+int get_soft_i2c_scl_pin(void);
+int get_soft_i2c_sda_pin(void);
+#endif
+#define CONFIG_SOFT_I2C_GPIO_SCL	get_soft_i2c_scl_pin()
+#define CONFIG_SOFT_I2C_GPIO_SDA	get_soft_i2c_sda_pin()
 
 /* POWER */
 #define CONFIG_POWER